Abstract: A method is provided to enable communication between a controller and a preamplifier in a storage device. For example, the method includes implementing a serial port which is configured to transmit digital signals between the controller and the preamplifier over a single bidirectional serial data line. The serial port is controlled to selectively transmit digital signals over the bidirectional serial data line in either a first direction from the controller to the preamplifier or a second direction from the preamplifier to the controller.

Abstract: A method is provided, for example, to implement multiplexed communication on an analog bus between a recording channel and a preamplifier in a storage device. A first input of read data circuitry within the recording channel is switchably connected to a first analog line of the analog bus to receive read data transmitted from the preamplifier to the recording channel over the first analog line during a read operation. In addition, a write data output of write data circuitry within the recording channel is switchably connected to the first analog line of the analog bus to transmit write data from the recording channel to the preamplifier over the first analog line during a write operation.

Abstract: A method is provided, for example, to implement multiplexed communication between a controller and a preamplifier in a storage device. For example, multiplexed communication is implemented by controlling a bidirectional serial data line of a digital bus to selectively transmit digital signals in either a first direction from the controller to the preamplifier or a second direction from the preamplifier to the controller, in response to a direction control signal, and concurrently transmitting a synchronous clock signal over a clock signal line of the digital bus from the controller to the preamplifier to synchronize transfer and processing of the digital signals transmitted on the bidirectional serial data line of the digital bus. The direction control signal is transmitted from the controller to the preamplifier on one of the bidirectional serial data line and the clock signal line of the digital bus.

Abstract: An apparatus for measuring cross-talk in an array reader magnetic storage system includes an array reader with multiple read heads operable to read data from a magnetic storage medium, a first preamplifier connected to a first read head, a second preamplifier connected to a second read head, and a cross-talk measurement circuit connected to the first preamplifier and to the second preamplifier, operable to measure cross-talk between a first signal from the first read head and a second signal from the second read head.

Abstract: An apparatus for measuring cross-talk in an array reader magnetic storage system includes an array reader with multiple read heads operable to read data from a magnetic storage medium, a first preamplifier connected to a first read head, a second preamplifier connected to a second read head, and a cross-talk measurement circuit connected to the first preamplifier and to the second preamplifier, operable to measure cross-talk between a first signal from the first read head and a second signal from the second read head.

Abstract: A switching power amplifier for multi-path signal interleaving includes a signal splitter configured to split a multi-bit source signal from a digital source into a plurality of multi-bit signals, one or more fractional delay filters configured to delay one or more signals of the plurality of signals by a selected time, a plurality of bit-stream converters, each bit-stream converter configured to receive one of the multi-bit signals, each bit-stream converter further configured to generate a single-bit signal based on a received multi-bit signal, a plurality of switching power amplifiers, each switching power amplifier configured to receive a single-bit signal from one of the bit-stream converters, and an interleaver configured to generate an interleaved output by interleaving two or more outputs of the switching power amplifiers, wherein a sampling frequency of the interleaved output of the interleaver is greater than the selected sampling frequency of the multi-bit source signal.

Abstract: A electronic circuit with low inductance connections is disclosed. The electronic circuit includes a ground plane and a flex circuit. The flex circuit having a first surface generally facing the ground plane and a second surface opposite to the first surface. The flex circuit also having a flexible bridge defined thereof. The electronic circuit further includes a first electronic device communicatively coupled to the second surface of the flex circuit, a second electronic device communicatively coupled to the second surface of the flex circuit, and at least one conductive trace defined on the second surface of the flex circuit and extending along the flexible bridge. One end of the at least one conductive trace is configured for receiving an outbound current from the first electronic device and another end of the at least one conductive trace is communicatively coupled to the second electronic device through a vertical interconnect access.

Abstract: The disclosure is directed to a system and method of a system and method for determining fundamental bit cell duration of a data record, which can be used for pattern-dependent write (PDW) current control. According to various embodiments of the disclosure, at least a first portion of a data record is fed through a plurality of delay units. A binary output of each delay unit is stored in at least one register when the delay units have received the first portion of the data record. The register contents are then decoded to determine fundamental bit cell duration of the data record based upon the stored binary outputs.

Abstract: A method and system for high density pulse density modulation is disclosed. In accordance with the present disclosure, a modulation function is split in to two band limited streams using a complementary pair of non-linear functions. More specifically, one bitstream definition contains the peaks of the original function while the other bitstream contains a soft clipping version of the original bitstream. The bitstreams are applied to a pair of switching amplifiers, and the bitstreams can be combined again to reconstruct the original function. The method in accordance with the present disclosure limits the amount of input power necessary to achieve higher output power, lowers operating voltage and improves power amplifier efficiency.

Abstract: Individual magneto-resistive read elements are connected to the pre-amplifier through a multi-conductor transmission line; one side of each magneto-resistive read element is taken to a single common lead which is also received in the read pre-amplifier. Amplification and bias control are performed by the read pre-amplifier. A low-noise input stage amplifier configuration accommodates a shared common lead in a multi-head environment. Means for independently biasing the magneto-resistive read elements are also provided. Feedback loops are employed to regulate the operating points of the input stages, and to set the potential of the common head terminal. Two-dimensional magnetic recording system testability is enhanced by ability to multiplex any head to a single system output.

Abstract: A bitstream generator includes at least first and second bitstream generator stages connected in a cascaded arrangement. The first bitstream generator stage includes a first adder which receives an input signal and generates a first error signal indicative of a difference between the input signal and a first bitstream candidate representing a closest approximation to the input signal among multiple bitstream candidates generated by the first bitstream generator stage. The second bitstream generator stage includes a second adder which receives the first error signal and generates a second error signal indicative of a difference between the first error signal and a second bitstream candidate representing a closest approximation to the input signal among multiple bitstream candidates generated by the second bitstream generator stage. A third adder in the bitstream generator receives the first and second bitstream candidates and generates an output signal more closely approximating the input signal.

Abstract: An amplification system and an integrated circuit include a bandpass filter and an amplifier. The bandpass filter filters an input digital bitstream or an amplified signal to provide a filtered signal. The bandpass filter exhibits constant input impedance over a passband associated with the input digital bitstream, and a stopband associated with shaped-noise energy, thereby increasing signal-to-noise ratio and/or signal-to-distortion ratio associated with the filtered signal. The amplifier amplifies at least one of the filtered signal and the input digital bitstream to provide the amplified signal. A method of providing amplification includes bandpass filtering an input digital bitstream or an amplified signal to provide a filtered signal, providing constant input impedance over a passband and a stopband by the bandpass filtering, and amplifying at least one of the filtered signal and the input digital bitstream to provide the amplified signal.

Abstract: The disclosure is directed to a system and method of a system and method for determining fundamental bit cell duration of a data record, which can be used for pattern-dependent write (PDW) current control. According to various embodiments of the disclosure, at least a first portion of a data record is fed through a plurality of delay units. A binary output of each delay unit is stored in at least one register when the delay units have received the first portion of the data record. The register contents are then decoded to determine fundamental bit cell duration of the data record based upon the stored binary outputs.

Abstract: In one embodiment, a power amplification system of a radio-frequency transmitter includes a digital signal source that provides a digital input signal to an interleaved-bit-stream generator, which outputs a digital switching signal to a switching power amplifier. The interleaved-bit-stream generator has an eight-path interleaving architecture that helps reduce the effective clock-rate requirements of the interleaved-bit-stream generator. The interleaved-bit-stream generator includes an array of fractional-delay filters for receiving the digital input signal and outputting eight fractionally delayed digital output signals to a bit-stream generation array adapted to output eight corresponding bit streams to a serializer block that interleaves and combines the eight bit-streams into the digital switching signal. The relative phases of the interleaved signals may be adjusted to achieve certain desired effects.

Abstract: A voltage-switched class-S amplifier circuit includes an output stage configured to receive at least one control signal and operative to generate an output signal as a function of the at least one control signal. The amplifier circuit further includes a driver circuit coupled with the output stage. The driver circuit is configured to receive an input bit stream signal and is operative to generate the control signal as a function of the input bit stream signal in such a manner that a common mode component is eliminated from the control signal.

Abstract: A composite amplifier providing digitally selectable amplification includes a plurality of channels and a combiner. Each of the channels includes a digitally controllable selector, a Class-S power amplifier, and bandpass filter. The digitally controllable selector selectively couples a digital bitstream to the amplifier. The amplifier receives the digital bitstream and provides an amplified signal. The bandpass filter generates a filtered signal as a function of the amplified signal. The combiner couples filtered signals provided by the channels to form a composite output signal.

Abstract: A storage system with pattern dependent write includes a magnetic write head, a magnetic storage medium, a read channel operable to process write data to be recorded on the magnetic storage medium by the magnetic write head, and a preamplifier operable to receive the write data and an associated clock from the read channel, to generate a pattern dependent write control signal based on a pattern in the write data and on the clock, and to set a write current level through the magnetic write head to a number of different current levels based on the pattern dependent write control signal.

Abstract: The disclosure is directed to a low noise amplifier (LNA) configuration that compensates for DC offsets of incoming signals from a magnetoresistive head. According to various embodiments, the LNA includes a shunt-feedback differential pair of amplifiers adaptively biased according to a detected input DC voltage offset of the incoming signals from the magnetoresistive head. The LNA is thus enabled to amplify the AC signal component substantially unaffected by the DC offset. The DC component in the LNA output signal is then removable via offset compensating circuitry located between the LNA and subsequent stages without significant signal-to-noise ratio (SNR) penalty.

Abstract: The invention may be embodied in radio frequency power amplifier (RF-PA) predriver circuits employing a hybrid analog/digital RF architecture including a resynchronizing digital-to-analog convertor to drive an efficient high-power output stage suitable for driving standard high power amplifier (HPA) output devices. The hybrid analog/digital RF architecture retains the advantages of high digital content integration found in conventional Class-S architecture, while relaxing the performance requirements on the output transistors and on the bitstream generator. The resulting predriver circuit combines the VLSI integration benefits of digital designs with the extensibility to arbitrary output power levels characteristic of analog designs. The hybrid analog/digital driving circuit is well suited for use with analog and Class-S HPAs used in wireless communication systems, such as the Doherty type HPA.

Abstract: In one embodiment, a power amplification system of a radio-frequency transmitter includes a digital signal source that provides a digital input signal to an interleaved-bit-stream generator, which outputs a digital switching signal to a switching power amplifier. The interleaved-bit-stream generator has an eight-path interleaving architecture that helps reduce the effective clock-rate requirements of the interleaved-bit-stream generator. The interleaved-bit-stream generator includes an array of fractional-delay filters for receiving the digital input signal and outputting eight fractionally delayed digital output signals to a bit-stream generation array adapted to output eight corresponding bit streams to a serializer block that interleaves and combines the eight bit-streams into the digital switching signal. The relative phases of the interleaved signals may be adjusted to achieve certain desired effects.