Patents by Inventor Ross William Keesler
Ross William Keesler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7240430Abstract: A method of forming a plurality of solid conductive bumps for interconnecting two conductive layers of a circuit board with substantially coplanar upper surfaces. The method comprises the steps of applying a continuous homogenous metal layer onto a dielectric substrate, applying a first photoresist and exposing and developing said first photoresist to define a pattern of conductive bumps, etching the metal layer exposed by said development to form said plurality of conductive bumps, removing said first photoresist, applying a second photoresist onto the metal layer, exposing and developing said second photoresist to define a pattern of conductive bumps and circuit lines; etching the metal layer exposed by said development to form a pattern of circuit lines in said metal layer; and removing said second photoresist. The methods of the present invention also provides for fabricating a multilayer circuit board and a metallic border for providing rigidity to a panel.Type: GrantFiled: January 5, 2005Date of Patent: July 10, 2007Assignee: International Business Machines CorporationInventors: Bernd Karl-Heinz Appelt, James Russell Bupp, Donald Seton Farquhar, Ross William Keesler, Michael Joseph Klodowski, Andrew Michael Seman, Gary Lee Schild
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Patent number: 6902869Abstract: A method of forming a plurality of solid conductive bumps for interconnecting two conductive layers of a circuit board with substantially coplanar upper surfaces. The method comprises the steps of applying a continuous homogenous metal layer onto a dielectric substrate, applying a first photoresist and exposing and developing said first photoresist to define a pattern of conductive bumps; etching the metal layer exposed by said development to form said plurality of conductive bumps; removing said first photoresist; applying a second photoresist onto the metal layer; exposing and developing said second photoresist to define a pattern of conductive bumps and circuit lines; etching the metal layer exposed by said development to form a pattern of circuit lines in said metal layer; and removing said second photoresist. The methods of the present invention also provides for fabricating a multilayer circuit board and a metallic border for providing rigidity to a panel.Type: GrantFiled: September 17, 2003Date of Patent: June 7, 2005Assignee: International Business Machines CorporationInventors: Bernd Karl-Heinz Appelt, James Russell Bupp, Donald Seton Farquhar, Ross William Keesler, Michael Joseph Klodowski, Andrew Michael Seman, Gary Lee Schild
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Patent number: 6739048Abstract: A process of fabricating a circuitized structure is provided. The process includes the steps of providing an organic substrate having circuitry thereon; applying a dielectric film on the organic substrate; forming microvias in the dielectric film; sputtering a metal seed layer on the dielectric film and the microvias; plating a metallic layer on the metal seed layer; and forming a circuit pattern thereon.Type: GrantFiled: January 27, 2000Date of Patent: May 25, 2004Assignee: International Business Machines CorporationInventors: Gerald Walter Jones, Ross William Keesler, Voya Rista Markovich, William John Rudik, James Warren Wilson, William Earl Wilson
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Publication number: 20040091821Abstract: A method of forming a plurality of solid conductive bumps for interconnecting two conductive layers of a circuit board with substantially coplanar upper surfaces. The method comprises the steps of applying a continuous homogenous metal layer onto a dielectric substrate, applying a first photoresist and exposing and developing said first photoresist to define a pattern of conductive bumps; etching the metal layer exposed by said development to form said plurality of conductive bumps; removing said first photoresist; applying a second photoresist onto the metal layer; exposing and developing said second photoresist to define a pattern of conductive bumps and circuit lines; etching the metal layer exposed by said development to form a pattern of circuit lines in said metal layer; and removing said second photoresist. The methods of the present invention also provides for fabricating a multilayer circuit board and a metallic border for providing rigidity to a panel.Type: ApplicationFiled: September 17, 2003Publication date: May 13, 2004Applicant: International Business Machines CorporationInventors: Bernd Karl-Heinz Appelt, James Russell Bupp, Donald Seton Farquhar, Ross William Keesler, Michael Joseph Klodowski, Andrew Michael Seman, Gary Lee Schild
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Patent number: 6684497Abstract: A method of forming a printed circuit board comprising a plurality of conductive bumps with substantially coplanar upper surfaces. The method comprises the steps of applying a metal layer onto a dielectric substrate; applying a first photoresist onto said substrate and exposing and developing said first photoresist to define a pattern of conductive bumps; etching the metal layer exposed by said development to form said plurality of conductive bumps; removing said first photoresist; applying a second photoresist onto the metal layer; exposing and developing said second photoresist to define a pattern of conductive bumps and circuit lines; etching the metal layer exposed by said development to form a pattern of circuit lines in said metal layer; and removing said second photoresist. The present invention is also provides a method for preparing a reinforced panel.Type: GrantFiled: February 20, 2001Date of Patent: February 3, 2004Assignee: International Business Machines CorporationInventors: Bernd Karl-Heinz Appelt, James Russell Bupp, Donald Seton Farquhar, Ross William Keesler, Michael Joseph Klodowski, Andrew Michael Seman, Gary Lee Schild
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Publication number: 20020078562Abstract: A process of fabricating a circuitized substrate is provided which comprising the steps of: providing an organic substrate having circuitry thereon; applying a dielectric film on the organic substrate; forming microvias in said dielectric film; sputtering a metal seed layer on the dielectric film and in said microvias; plating a metallic layer on the metal seed layer; and forming a circuit pattern thereon.Type: ApplicationFiled: January 27, 2000Publication date: June 27, 2002Inventors: Gerald Walter Jones, Ross William Keesler, Voya Rista Markovich, William John Rudik, James Warren Wilson, William Earl Wilson
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Publication number: 20010032828Abstract: A method for forming a printed circuit board comprising a plurality of conductive bumps having substantially coplanar upper surfaces is provided. The method comprises: forming a substantially planar metallic layer having a first thickness on at least one surface of the dielectric; applying a first photoresist on the metal layer; imaging the first photoresist to define a pattern of conductive bumps; etching the exposed portions of the metal layer to a second thickness to form the conductive bumps; removing the first photoresist; applying a second photoresist to the metal layer; imaging the second photoresist to define a pattern of circuitry; etching the exposed portions of the metal layer to provide the electrical circuitry; and removing the second photoresist. The present invention also provides a method for preparing printed circuit boards wherein two conductive layers that are disposed on opposing sides of a dielectric layer are inter-connected by at least one of the substantially coplanar conductive bumps.Type: ApplicationFiled: February 20, 2001Publication date: October 25, 2001Applicant: International Business Machines CorporationInventors: Bernd Karl-Heinz Appelt, James Russell Bupp, Donald Seton Farquhar, Ross William Keesler, Michael Joseph Klodowski, Andrew Michael Seman, Gary Lee Schild
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Patent number: 6222136Abstract: A printed circuit board comprising a plurality of conductive bumps having substantially coplanar upper surfaces is provided. The circuit board is formed by providing: a substantially planar metallic layer having a first thickness on at least one surface of the dielectric; applying a first photoresist on the metal layer; imaging the first photoresist to define a pattern of conductive bumps; etching the exposed portions of the metal layer to a second thickness to form the conductive bumps; removing the first photoresist; applying a second photoresist to the metal layer; imaging the second photoresist to define a pattern of circuitry; etching the exposed portions of the metal layer to provide the electrical circuitry; and removing the second photoresist. The present invention also provides a method for preparing printed circuit boards wherein two conductive layers that are disposed on opposing sides of a dielectric layer are inter-connected by at least one of the substantially coplanar conductive bumps.Type: GrantFiled: November 12, 1997Date of Patent: April 24, 2001Assignee: International Business Machines CorporationInventors: Bernd Karl-Heinz Appelt, James Russell Bupp, Donald Seton Farquhar, Ross William Keesler, Michael Joseph Klodowski, Andrew Michael Seman, Gary Lee Schild
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Patent number: 6131279Abstract: A process of fabricating a circuitized substrate is provided which comprising the steps of: providing an organic substrate having circuitry thereon; applying a dielectric film on the organic substrate; forming microvias in said dielectric film; sputtering a metal seed layer on the dielectric film and in said microvias; plating a metallic layer on the metal seed layer; and forming a circuit pattern thereon.Type: GrantFiled: January 8, 1998Date of Patent: October 17, 2000Assignee: International Business Machines CorporationInventors: Gerald Walter Jones, Ross William Keesler, Voya Rista Markovich, William John Rudik, James Warren Wilson, William Earl Wilson
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Patent number: 6027858Abstract: A process of tenting plated through holes with a photoimageable dielectric is provided which includes a dielectric film comprising a photoimageable epoxy based resin layer and a peelable polyester layer. In accordance with the process of the present invention, the peelable polyester layer of the dielectric film is removed prior to baking, developing, patterning or curing the structure.Type: GrantFiled: June 6, 1997Date of Patent: February 22, 2000Assignee: International Business Machines CorporationInventors: Gerald Walter Jones, Ross William Keesler, Voya Rista Markovich, Heinke Marcello, James Warren Wilson, William Earl Wilson