Abstract: There is a test structure on a semiconductor substrate for testing misalignment between adjacent implanted regions of opposite conductivity in a semiconductor device. In an example embodiment, the test structure includes a first and a second triple well structure; the second triple well structure is adjacent to the first triple well-structure in a first direction. Each structure includes a lower buried n-well region, a p-well region, a p+-region, an n-well region and a base n+-region, wherein a central base portion and a central n-well region portion are common to the first and the second structure, with the central base portion as a symmetry line with a width. Between the central base portion and the p-well region in the first triple well-structure a first overlay, and between the central base portion and the p-well region in the second triple well-structure a second overlay is provided.

Abstract: Semiconductor device having on a single substrate (1) at least one memory cell (3) and at least one logic transistor (25); the at least one memory cell having a floating gate (5), a tunnel oxide layer (11) between the floating gate and the substrate (1), a control gate (15), and a control oxide layer (13) between the control gate (15) and the floating gate (5); the at least one logic transistor (25) having a logic transistor gate (5′, 15″) and a logic transistor gate oxide (11″) between the logic transistor gate (5′, 15″) and the substrate (1), the tunnel oxide layer (11) of the memory cell (3) and the logic transistor gate oxide (11″) having a same or substantially same predetermined first thickness. The invention also relates to a method of manufacturing such a device and to such a device that also comprises a high voltage transistor (17) which is optionally made so as to be an integral part of at least the memory cell (3).

Abstract: Test structure (1), on a semiconductor substrate, for testing misalignment between adjacent implanted regions of opposite conductivity in a semiconductor device, including a first (T1) and a second (T2) triple well-structure, the second triple well-structure (T2) adjacent to the first triple well-structure (T1) in a first direction (D1), each structure (T1; T2) including a lower buried n-well region, a p-well region, a p+-region, an n-well region and a base n+-region,

Abstract: Semiconductor device having on a single substrate (1) at least one memory cell (3) and at least one logic transistor (25);

Abstract: Semiconductor device having on a single substrate (1) at least one memory cell (3) and at least one logic transistor (25);