Abstract: The present invention provides a structured integrated circuit design methodology. The methodology is based on describing a two-phase logic function using a high level behavioral description flow chart, properly sizing devices to be used in the circuit for speed and reducing trial and error in circuit layout implementation using novel chip planning techniques. The methodology begins with the definition of signal types based on the circuit function that creates a particular signal and the type of input signal that feeds the circuit function. A rigid set of rules is then established for use of the signal types. Next the technical specification of the two-phase logic function is defined and utilized to create a behavioral flow chart using defined symbols. An associated database of corresponding Boolean equations is then created that defines the parameters of the various elements of the flow chart.

Abstract: Each cell of a static latch implemented in MOS transistor circuitry includes an MOS transistor configured to operate a depletion mode and operably coupled to communicate an output node of the cell to an input node of the cell in absence of a control signal, to effect the latching operation. Presence of the control signal allows data to be efficiently written to the cell by enabling a transfer gate to establish a communication path for the data to the input node of the cell, while at the same time disabling the MOS transistor to terminate communication of the output node of the cell to its input node during the write operation.

Abstract: An improved strobe line driver circuit is disclosed that generates a plurality of strobe signals in response to a corresponding plurality of enable signals and a first clock signal. The circuit includes a clock enable transistor that generates a second clock signal. The circuit also includes a plurality of transistor pairs coupled to the first and second clock signals. Each transistor pair receives one enable signal and generates a corresponding strobe signal.

Abstract: An error correcting network adapted for encoding and decoding data transferred to and from a bubble memory has parallel linear encoder/decoder circuits. An error syndrome generated in response to a parity error in an initial read operation is used by one encoder/decoder circuit for correcting the parity error during a subsequent reread of the data. The error syndrome is also stored in a latch for comparison with a second error syndrome generated in response to the data during the reread operation. A true comparison between the two error syndromes verifies that that data has not changed between the two read operations due to a soft error and that the error correction of the first encoder/decoder circuit is valid.

Abstract: A digital watch including a clocking signal generator is disclosed wherein a control circuit provides phasing signals for multiplexing data representing seconds, minutes, hours, and data information in successive cycles to a visual display panel. In the normal mode of operation of the watch, minutes and hours are displayed. The watch further includes circuitry for selectively displaying seconds and date information as well as for setting the hours, minutes, and date. The aforementioned functions require the utilization of only three functional switches which may be incorporated into a stem of the watch. By selectively closing and opening one switch, as for example, pushing in and releasing the stem, seconds information is first displayed and then the date information is momentarily displayed for a predetermined interval after which the watch returns to a normal mode of operation of displaying hours and minutes.

Abstract: A digital watch including a clocking signal generator is disclosed wherein a control circuit provides phasing signals for multiplexing data representing seconds, minutes, hours, and date information in successive cycles to a visual display panel. In the normal mode of operation of the watch, minutes and hours are displayed. The watch further includes circuitry for selectively displaying seconds and date information as well as for setting the hours, minutes, and date. The aforementioned functions require the utilization of only three functional switches which may be incorporated into a stem of the watch. By selectively closing and opening one switch, as for example, pushing in and releasing the stem, seconds information is first displayed and then the date information is momentarily displayed for a predetermined interval after which the watch returns to a normal mode of operation of displaying hours and minutes.