Abstract: Methods for the production of a semiconductor device are disclosed. In one embodiment, a method may include: (1) mechanically contacting a first substrate (100) having a semiconductor material to a second substrate (200) having a bondable passivation material and contact vias (210) extending through the bondable passivation material; (2) covering the contact vias (210) with an at least high-resistance material (220, 300) on a side facing away from the first substrate (100); (3) applying an electric potential between the at least high-resistance material and the first substrate. The potential has a sufficient level that is functionally sufficient to initiate a bonding process between the bondable passivation material of the second substrate and the semiconductor material of the first substrate.

Abstract: A method is provided for producing at least one electrical via in a substrate, the method comprising: producing a protective layer over a component structure which has been produced or is present on a front side of the substrate; forming at least one contact hole which extends from a surface of a backside of the substrate to a contact surface of the component structure; forming a metal-containing and thus conductive lining in the at least one contact hole creating a hollow electrically conductive structure in the at least one contact hole; and applying a passivation layer over the backside of the substrate, the passivation layer spanning over the hollow electrically conductive structure for forming the at least one electrical via. Also provided is a micro-technical component comprising at least one electrical via.

Abstract: A semiconductor device comprising a first substrate (100) including silicon may include a bondable passivation (200) made of a bondable material, especially a glass material; at least one contact via (210) extending through the passivation and contacting a region of the first substrate (100); an interface (204) created by anodic bonding between the substrate including silicon and the bondable passivation (200), wherein silicon-oxygen-silicon bonds are formed in the interface in order to provide adhesion between the passivation (200) and the substrate (100)

Abstract: Anodic bonding method are disclosed. In one embodiment, an anodic bonding method may include: (1) providing a first substrate (100) having a semiconductor material; (2) providing a second substrate (200) having a bondable passivation material and contact vias (210); (3) contacting the first substrate and the second substrate (100, 200); (4) providing a resistance layer (300, 220) on the second substrate (200); and (5) applying a potential between the resistance layer and the first substrate.

Abstract: Concepts as well as arrangements are suggested, according to which a bond is enabled by anodic bonding between a glass substrate (200) having contact vias (210) and a substrate (100) including a semiconductor. For this purpose, a cover of the contact vias (210) is provided during the anodic bonding method such that process conditions are created that achieve a reliable and robust bonding of the substrates. A high resistance can be provided in the region of the contact vias (210). The arrangement for contacting the semiconductor device to the silicon substrate (100) having at least one contact via (210) extending through the passivation in order to contact a region of the first substrate (100).

Abstract: A method is provided for producing at least one electrical via in a substrate, the method comprising: producing a protective layer over a component structure which has been produced or is present on a front side of the substrate; forming at least one contact hole which extends from a surface of a backside of the substrate to a contact surface of the component structure; forming a metal-containing and thus conductive lining in the at least one contact hole creating a hollow electrically conductive structure in the at least one contact hole; and applying a passivation layer over the backside of the substrate, the passivation layer spanning over the hollow electrically conductive structure for forming the at least one electrical via. Also provided is a micro-technical component comprising at least one electrical via.

Abstract: A method is provided for producing at least one electrical via in a substrate, the method comprising: producing a protective layer over a component structure which has been produced or is present on a front side of the substrate; forming at least one contact hole which extends from a surface of a backside of the substrate to a contact surface of the component structure; forming a metal-containing and thus conductive lining in the at least one contact hole creating a hollow electrically conductive structure in the at least one contact hole; and applying a passivation layer over the backside of the substrate, the passivation layer spanning over the hollow electrically conductive structure for forming the at least one electrical via. Also provided is a micro-technical component comprising at least one electrical via.

Abstract: A method is provided for producing at least one electrical via in a substrate, the method comprising: producing a protective layer over a component structure which has been produced or is present on a front side of the substrate; forming at least one contact hole which extends from a surface of a backside of the substrate to a contact surface of the component structure; forming a metal-containing and thus conductive lining in the at least one contact hole creating a hollow electrically conductive structure in the at least one contact hole; and applying a passivation layer over the backside of the substrate, the passivation layer spanning over the hollow electrically conductive structure for forming the at least one electrical via. Also provided is a micro-technical component comprising at least one electrical via.

Abstract: The invention relates to a process for and an arrangement of the connection of processed semiconductor wafers (1, 2) wherein, in addition to the firm connection, there is an electric connection (5) between the semiconductor wafers and/or the electronic structures (3) supporting them. For this purpose, low-melting structured intermediate glass layers (6; 6a) are used as insulating layers and as an electric connection in the form of electrically conductive solder (5) on a glass basis in order to achieve a firm connection.

Abstract: Disclosed are methods and microsystems for vertically through-plating (6) cover plates (5) for microsystem components (2, 2a) by means of a conductive solder glass (8). Said methods and microsystems make it possible to simplify through-plating, reduce the failure rate, and increase reliability.

Abstract: For bonding a donor wafer (1) and a system wafer (9) an edge bead (3) of an epitaxial layer (2) on the donor wafer is flattened or completely removed by etching so that a reliable contact after bonding up to the edge region (5, 6) is possible. The etching mask is produced by means of a resist layer (4) as well as by means of removal of resist at the edge, free exposure and developing without a special photomask.

Abstract: The invention relates to a method and a through-vapor mask for depositing layers in a structured manner by means of a specially designed coating mask which has structures that accurately fit into complementary alignment structures of the microsystem wafer to be coated in a structured manner such that the mask and the wafer can be accurately aligned relative to one another. Very precisely defined portions on the microsystem wafer are coated through holes in the coating mask, e.g. by mans of sputtering, CVD, or to evaporation processes.

Abstract: The invention relates to a method for selective material deposition for sensitive structures in micro systems technology for producing mechanical adjustment structures (6, 5) for a vapour penetration mask (8), the adjustment structures on the component disc (7) and the mask being created using the same structuring method. Complementary adjustment structures can be produced thereon with a very high degree of precision. KOH etching in silicon can be used in order to create equally inclined flanks (2, 2a) in a depression and a complementary protrusion.

Abstract: The invention relates to a method for producing semiconductor substrates by bonding. The aim of said method is to reduce the non-usable edge region on the bonded wafer component and to improve the edge geometry of the wafer composite. This is achieved by a method for joining two semiconductor wafers using a semiconductor wafer bonding process. The surfaces of the two semiconductor wafers that are to be bonded are provided with a border or edge geometry that has a special short front-end facet. After the bonding process, one of the two wafers is ablated to obtain an edge region that is as devoid as possible of defects and a usable wafer surface that is as large as possible.

Abstract: Disclosed are methods and microsystems for vertically through-plating (6) cover plates (5) for microsystem components (2, 2a) by means of a conductive solder glass (8). Said methods and microsystems make it possible to simplify through-plating, reduce the failure rate, and increase reliability.

Abstract: The invention relates to a method and arrangement for carrying out the nondestructive determination of the connection quality of bonded wafers (1, 8) in order to verify the connection strength. The fact that an unbonded region (9) forms around a raised or recessed structure (3) on at least one of the connecting surfaces is made use of. The extension of the unbonded region is a measure of the strength of the wafer connection and is electrically determined by staggered contacts (5, 4) that, with the formation of the bond connection, close, only in part, via a contact strip (10).

Abstract: The invention relates to a method for producing semiconductor substrates by bonding. The aim of said method is to reduce the non-usable edge region on the bonded wafer component and to improve the edge geometry of the wafer composite. This is achieved by a method for joining two semiconductor wafers using a semiconductor wafer bonding process. The surfaces of the two semiconductor wafers that are to be bonded are provided with a border or edge geometry that has a special short front-end facet. After the bonding process, one of the two wafers is ablated to obtain an edge region that is as devoid as possible of defects and a usable wafer surface that is as large as possible.

Abstract: The invention relates to a process for and an arrangement of the connection of processed semiconductor wafers (1, 2) wherein, in addition to the firm connection, there is an electric connection (5) between the semiconductor wafers and/or the electronic structures (3) supporting them. For this purpose, low-melting structured intermediate glass layers (6; 6a) are used as insulating layers and as an electric connection in the form of electrically conductive solder (5) on a glass basis in order to achieve a firm connection.

Abstract: The invention relates to a method and arrangement for carrying out the nondestructive determination of the connection quality of bonded wafers (1, 8) in order to verify the connection strength. The fact that an unbonded region (9) forms around a raised or recessed structure (3) on at least one of the connecting surfaces is made use of. The extension of the unbonded region is a measure of the strength of the wafer connection and is electrically determined by staggered contacts (5, 4) that, with the formation of the bond connection, close, only in part, via a contact strip (10).

Abstract: The inventive method enables chips (1) to be separated without damaging them, which have exposed sensitive micromechanical structures, from the group of wafers by means of standard parting-off grinding processes. During the parting-off grinding process, the micromechanical structures are covered with a thermofilm (4) thereby protecting them. The parting-off grinding, referred to as cutting (6) for short, ensues from the front side of the wafer with the aid of cutting marks (5) on the wafer. During this, the protective film (4) is completely cut through. After cutting, heat is used to detach the protective film from the separated chips (8) without leaving remnants thereon and without force acting upon the micromechanical structures. The separated chips are held by a supporting film onto which the semiconductor wafer is drawn before the cutting step (6). The properties of the supporting film are not modified during the heat treatment of the protective film.