Abstract: The invention relates to compositions and methods for making and using recombinant bacteria that are capable of regulated attenuation and/or regulated expression of one or more antigens of interest.

Abstract: Multiple graphics processor system and method embodiments are disclosed. One system embodiment, among others, comprises a multiple graphics processor system, comprising a first graphics processing unit having first status information and a second graphics processing unit having second status information, and first key logic corresponding to the first graphics processing unit, the first key logic configured to compare the first and second status information and communicate to the first graphics processing unit a key corresponding to the lowest completed stage of processing among the first and second graphics processing units.

Abstract: A method for a graphics processing unit (“GPU”) to maintain a local cache to minimize system memory reads is provided. A display read request and a logical address are received. The GPU determines whether a local cache contains a physical address corresponding to the logical address. If not, a cache fetch command is generated, and a number of cache lines is retrieved from a table, which may be a GART table, in the system memory. The logical address is converted to a corresponding physical address of the memory when the cache lines are retrieved from the table so that data in memory may be accessed by the GPU. When a cache line in the local cache is consumed, a next line cache fetch request is generated to retrieve a next cache line from the table so that the local cache maintains a predetermined amount of cache lines.

Abstract: An improved target and initiator. The initiator provides a starting address and length information on a bus synchronously with a clock signal. While the starting address and length information are present on the bus, the initiator provides a write or a read request signal that is activated and deactivated synchronously. The initiator then receives from the target unit a grant signal that is activated and deactivated synchronously. After the grant signal is deactivated, for a write operation, the initiator provides a number of write data items on the bus synchronously for capture by the target unit. For a read operation, the target provides a number of read data items on the bus synchronously for capture by the initiator unit. One data item provided in each clock cycle of the clock signal and the number of data items is determined by the length information provided.