Patents by Inventor Roy Kriss
Roy Kriss has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10387074Abstract: Communication apparatus includes multiple ports configured to serve as ingress ports and egress ports for connection to a packet data network. A memory is coupled to the ports and configured to contain both respective input buffers allocated to the ingress ports and a shared buffer holding data packets for transmission in multiple queues via the egress ports. Control logic is configured to monitor an overall occupancy level of the memory, and when a data packet is received through an ingress port having an input buffer that is fully occupied while the overall occupancy level of the memory is below a specified maximum, to allocate additional space in the memory to the input buffer and to accept the received data packet into the additional space.Type: GrantFiled: May 23, 2016Date of Patent: August 20, 2019Assignee: Mellanox Technologies TLV Ltd.Inventors: Roy Kriss, Barak Gafni, George Elias, Eran Rubinstein, Shachar Bar Tikva
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Patent number: 10069701Abstract: Communication apparatus includes multiple ports configured to serve as ingress ports and egress ports for connection to a packet data network. A single memory array is coupled to the ports and configured to contain both a respective headroom allocation for each ingress port and a shared buffer holding data packets for transmission in multiple queues via the egress ports. Control logic is configured to adjustably allocate to each ingress port a respective volume of memory within the single memory array to serve as the respective headroom allocation, and to queue the data packets in the multiple queues in the single memory array for transmission through the egress ports.Type: GrantFiled: January 13, 2016Date of Patent: September 4, 2018Assignee: MELLANOX TECHNOLOGIES TLV LTD.Inventors: George Elias, Barak Gafni, Shachar Bar Tikva, Roy Kriss, Eran Rubinstein
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Patent number: 10057017Abstract: Communication apparatus includes an input circuit, which receives a sequence of symbols arranged in a series of data blocks, including data symbols that encode the data and forward error correction (FEC) symbols that encode an error correction code. The input circuit decodes the data encoded by the data symbols and passes the decoded data to a buffer for output to a data link layer interface irrespective of the FEC symbols. An error correction circuit receives the data and the error correction code from the input circuit, and upon detecting an error in a given data block in the series, passes the corrected data from the given data block to the buffer for output to the data link layer interface in place of the data from the given data block that the input circuit decoded and passed to the buffer.Type: GrantFiled: March 28, 2017Date of Patent: August 21, 2018Assignee: MELLANOX TECHNOLOGIES TLV LTD.Inventors: Liron Mula, Ran Ravid, Oded Wertheim, Ran Sela, Roy Kriss
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Publication number: 20170337010Abstract: Communication apparatus includes multiple ports configured to serve as ingress ports and egress ports for connection to a packet data network. A memory is coupled to the ports and configured to contain both respective input buffers allocated to the ingress ports and a shared buffer holding data packets for transmission in multiple queues via the egress ports. Control logic is configured to monitor an overall occupancy level of the memory, and when a data packet is received through an ingress port having an input buffer that is fully occupied while the overall occupancy level of the memory is below a specified maximum, to allocate additional space in the memory to the input buffer and to accept the received data packet into the additional space.Type: ApplicationFiled: May 23, 2016Publication date: November 23, 2017Inventors: Roy Kriss, Barak Gafni, George Elias, Eran Rubinstein, Shachar Bar Tikva
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Publication number: 20170201469Abstract: Communication apparatus includes multiple ports configured to serve as ingress ports and egress ports for connection to a packet data network. A single memory array is coupled to the ports and configured to contain both a respective headroom allocation for each ingress port and a shared buffer holding data packets for transmission in multiple queues via the egress ports. Control logic is configured to adjustably allocate to each ingress port a respective volume of memory within the single memory array to serve as the respective headroom allocation, and to queue the data packets in the multiple queues in the single memory array for transmission through the egress ports.Type: ApplicationFiled: January 13, 2016Publication date: July 13, 2017Inventors: George Elias, Barak Gafni, Shachar Bar Tikva, Roy Kriss, Eran Rubinstein
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Publication number: 20170201350Abstract: Communication apparatus includes an input circuit, which receives a sequence of symbols arranged in a series of data blocks, including data symbols that encode the data and forward error correction (FEC) symbols that encode an error correction code. The input circuit decodes the data encoded by the data symbols and passes the decoded data to a buffer for output to a data link layer interface irrespective of the FEC symbols. An error correction circuit receives the data and the error correction code from the input circuit, and upon detecting an error in a given data block in the series, passes the corrected data from the given data block to the buffer for output to the data link layer interface in place of the data from the given data block that the input circuit decoded and passed to the buffer.Type: ApplicationFiled: March 28, 2017Publication date: July 13, 2017Inventors: Liron Mula, Ran Ravid, Oded Wertheim, Ran Sela, Roy Kriss
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Patent number: 9673934Abstract: Communication apparatus includes a PHY interface, which is configured to receive over a communication link and to decode a sequence of symbols arranged in a series of data blocks. The PHY interface includes an error correction circuit, which when actuated, corrects errors in decoded data symbols using FEC symbols in the data blocks. The decoded data include data packets containing respective error detection codes. A memory buffers the data blocks received by the PHY interface. A data link layer interface receives the data packets from the PHY interface, checks the data packets using respective error detection codes, and upon detecting an error in a given data packet, signals the PHY interface to read from the memory at least one buffered data block that contains the given data packet while actuating the error correction circuit to correct the error using the FEC symbols in the at least one buffered data block.Type: GrantFiled: September 30, 2015Date of Patent: June 6, 2017Assignee: MELLANOX TECHNOLOGIES TLV LTD.Inventors: Liron Mula, Ran Ravid, Oded Wertheim, Ran Sela, Roy Kriss
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Publication number: 20170093526Abstract: Communication apparatus includes a PHY interface, which is configured to receive over a communication link and to decode a sequence of symbols arranged in a series of data blocks. The PHY interface includes an error correction circuit, which when actuated, corrects errors in decoded data symbols using FEC symbols in the data blocks. The decoded data include data packets containing respective error detection codes. A memory buffers the data blocks received by the PHY interface. A data link layer interface receives the data packets from the PHY interface, checks the data packets using respective error detection codes, and upon detecting an error in a given data packet, signals the PHY interface to read from the memory at least one buffered data block that contains the given data packet while actuating the error correction circuit to correct the error using the FEC symbols in the at least one buffered data block.Type: ApplicationFiled: September 30, 2015Publication date: March 30, 2017Inventors: Liron Mula, Ran Ravid, Oded Wertheim, Ran Sela, Roy Kriss
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Patent number: 9584429Abstract: A method for communication includes storing packets received from a sending node over a communication link in a receive buffer of a receiving node. The receive buffer includes one or more blocks having a first block size. A first credit count, corresponding to a number of available blocks in the receive buffer, is derived. The first credit count is converted to a second credit count so as to represent an available space in the receive buffer in accordance with a second block size, which is different from the first block size. A transmission rate of the sending node is controlled by publishing the second credit count to the sending node over the communication link.Type: GrantFiled: July 21, 2014Date of Patent: February 28, 2017Assignee: MELLANOX TECHNOLOGIES LTD.Inventors: Zachy Haramaty, Roy Kriss, Noam Katz Abramovich, George Elias, Ran Ravid
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Publication number: 20160021016Abstract: A method for communication includes storing packets received from a sending node over a communication link in a receive buffer of a receiving node. The receive buffer includes one or more blocks having a first block size. A first credit count, corresponding to a number of available blocks in the receive buffer, is derived. The first credit count is converted to a second credit count so as to represent an available space in the receive buffer in accordance with a second block size, which is different from the first block size. A transmission rate of the sending node is controlled by publishing the second credit count to the sending node over the communication link.Type: ApplicationFiled: July 21, 2014Publication date: January 21, 2016Inventors: Zachy Haramaty, Roy Kriss, Noam Katz Abramovich, George Elias, Ran Ravid
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Patent number: 8989011Abstract: A method for communication includes, in a sender node that sends packets to a receiver node over a physical link, making a decision, for a packet that is associated with a respective virtual link selected from among multiple virtual links, whether the receiver node is to buffer the packet in a dedicated buffer assigned to the respective virtual link or in a shared buffer that is shared among the multiple virtual links. The packet is sent, and the decision is signaled, from the sender node to the receiver node.Type: GrantFiled: March 14, 2013Date of Patent: March 24, 2015Assignee: Mellanox Technologies Ltd.Inventors: Ran Ravid, Zachy Haramaty, Roy Kriss, Oded Wertheim
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Publication number: 20140269711Abstract: A method for communication includes, in a sender node that sends packets to a receiver node over a physical link, making a decision, for a packet that is associated with a respective virtual link selected from among multiple virtual links, whether the receiver node is to buffer the packet in a dedicated buffer assigned to the respective virtual link or in a shared buffer that is shared among the multiple virtual links. The packet is sent, and the decision is signaled, from the sender node to the receiver node.Type: ApplicationFiled: March 14, 2013Publication date: September 18, 2014Applicant: MELLANOX TECHNOLOGIES LTD.Inventors: Ran Ravid, Zachy Haramaty, Roy Kriss, Oded Wertheim