Abstract: An output buffer utilizes capacitive feedback to control the output slew rate largely independent of load capacitance. The invention slows the rising and falling slew rates and via a capacitance feedback reduces the effect of load capacitance on slew rate, and uses no DC current. Transistor switches are employed to isolate and reduce noise and interaction among the circuit components and functions.

Abstract: A circuit that automatically, seamlessly connects the higher (or the lower) of two power supplies to an output is described. The circuit does not incur a one diode drop when the two power supplies are at about the same voltage levels, and the unused power supply draws no stand-by current. Cross coupled transistor and cross coupled inverters are employed.

Abstract: An output buffer utilizes capacitive feedback to control the output slew rate largely independent of load capacitance. The invention slows the rising and falling slew rates and via a capacitance feedback reduces the effect of load capacitance on slew rate, and uses no DC current. Transistor switches are employed to isolate and reduce noise and interaction among the circuit components and functions.

Abstract: A circuit that automatically, seamlessly connects the higher (or the lower) of two power supplies to an output is described. The circuit does not incur a one diode drop when the two power supplies are at about the same voltage levels, and the unused power supply draws no stand-by current. Cross coupled transistor and cross coupled inverters are employed.

Abstract: A circuit is described that when the power supply to circuits that control a pass transistor is at zero volts, the pass transistor configured as a voltage level translator remains off regardless of the voltages and changes in voltages at the ports connected to the pass transistor. Cross coupled transistors provide a mechanism where the higher of the port voltages is available to power circuitry that maintains the control input of the pass transistor in the off condition. The voltages at the ports may rise and fall relative to each other, but the control input of the pass transistor will keep the pass transistor off.

Abstract: A circuit is described that when the power supply to circuits that control a pass transistor is at zero volts, the pass transistor configured as a voltage level translator remains off regardless of the voltages and changes in voltages at the ports connected to the pass transistor. Cross coupled transistors provide a mechanism where the higher of the port voltages is available to power circuitry that maintains the control input of the pass transistor in the off condition. The voltages at the ports may rise and fall relative to each other, but the control input of the pass transistor will keep the pass transistor off.

Abstract: The invention is directed to an apparatus and a method for generating a fault detection signal when a differential signal is in a fault condition. The fault condition arises when the data transmission path in a differential signaling device is either open, shorted, or terminated by an abnormal means, and is such that the inputs are within the valid common-mode range and a valid differential signal cannot be obtained. The invention is buffered from the differential signal source, and an intermediate signal is produced in response to the differential signal. Portions of the intermediate signal are compared to a reference signal, and based on the comparisons, fault condition control signals are produced. A fault detection signal is produced when two fault condition control signals indicate the presence of a fault. The fault detection signal is made available for invocation of a failsafe state.

Abstract: A low voltage differential swing (LVDS) signal driver having a constant output differential voltage (Vod) over variations in circuit fabrication processes, power supply voltages and operating temperatures (PVT). The minimum and maximum values of the LVDS output signal are monitored and, based upon the difference between them, a signal is provided to the circuit to control the LVDS output signal such that its peak-to-peak value is maintained at a determined value.

Abstract: A power-up circuit with hysteretic characteristics for regulating the activation of one or more output buffers of an extended logic circuit. The hysteresis of the power-up circuit of the invention permits turn on of a switching transistor of the circuit at one threshold voltage level and maintains the active state of that switching transistor until a second lower threshold voltage level. The hysteresis is achieved by providing two separate and electrically isolated control paths that are connected to the control node of the switching transistor. The first control path includes a plurality of diode devices designed to regulate the power supply level required to turn on the switching transistor. The second control path also includes diode devices but in lesser numbers so that, once the switching transistor is turned on by the first control path, it remains on in spite of fluctuations at the power supply rail.

Abstract: An enhanced bipolar-transistor apparatus for protecting electronic devices from electrostatic discharge damage. The apparatus is built around a bipolar transistor coupled between a power rail and the circuit to be protected. The protection is based on the high-current-capacity path through the bipolar transistor which is opened up either by collector-to-emitter punch-through in the bipolar transistor or by the bipolar transistor going into normal conduction upon being turned on by a switch coupled to the base of the bipolar transistor. In the preferred embodiment the switch is a MOS transistor that is designed to undergo source-to-drain breakdown at a fixed threshold voltage, whereupon it activates the bipolar transistor which in turn discharges the overvoltage.

Abstract: A circuit for translating logic signals from circuits supplied by one high-potential power rail to circuits supplied by another high-potential power rail in which the potentials of the two high-potential rails are not equal. The translator of the present invention is utilized in the transition from a 3V-supplied circuit to a 5V-supplied circuit, or vice versa, without any static current I.sub.CCt and regardless of the power-up sequencing. The static current is eliminated by isolating the output of the first stage of the translator, which is at the first high-potential power rail level, from all transistors of the second stage that are tied directly to the second high-potential power rail. In the preferred embodiment of the invention the transistors of the second stage that are powered by the second high-potential power rail are PMOS transistors and the isolation is achieved by linking those PMOS transistors to the first stage through a series of controlling NMOS transistors.

Abstract: A BICMOS input buffer circuit (20) incorporates an integral CMOS passgate circuit (P2,N2) between bipolar input (Q1) and output (Q3,Q4,Q5) transistors of the input buffer circuit. Latch enable inputs (LE) receive latch enable signals for operating the input buffer circuit and internal passgate in a transparent mode for passing data signals from the input (V.sub.IN) to the output (V.sub.OUT) and in a blocking mode for blocking data signals. The internal CMOS passgate circuit (P2,N2) is coupled into the input buffer circuit (20) to control nodes of the transistor output pullup (Q4,Q5) and pulldown (Q3) for controlling the conducting states of the respective transistor output pullup and pulldown to implement the blocking and transparent modes. A third passgate transistor (P3) may also be coupled between a control node (m1) of the transistor output pullup (Q4,Q5) and the low potential power rail (GND) for positive turn off of the output pullup.

Abstract: A circuit to be used with tristate output buffers as a means of diverting from the output pulldown transistor control nodes Miller Current arising while the output buffer is being switched from the low-active state L to the inactive state Z. The circuit complements a DC Miller Killer circuit, relieving the latter from having to deal with this transient, and hence permitting a down-sizing of the DCMK transistor. The net effect is a significantly faster L.fwdarw.Z transition for the tristate buffer and a slightly faster Z.fwdarw.L transition, all accomplished without degrading the DC Miller Killer protection against L.fwdarw.H bus transitions.The key to the present invention is its use of the time interval between the respective, sequential switching of the enable buffer outputs, E and EB following the application of a disable signal to this enable buffer. The present invention includes circuitry which ensures that its Miller Killer transistor is conducting only during the transient associated with the L.

Abstract: A BICMOS output buffer circuit delivers output signals of high and low potential levels at an output (V.sub.OUT) in response to data signals at an input (V.sub.IN). A CMOS output pulldown driver transistor (Q60) sources base drive current to a relatively large current conducting bipolar primary output pulldown transistor (Q44). A relatively small current conducting CMOS secondary output pulldown transistor (Q60A) is coupled with primary current path in parallel with the primary current path of the bipolar primary output pulldown transistor (Q44) between the output (V.sub.OUT) and low potential power rail (GNDN). The control gate node of CMOS secondary output pulldown transistor (Q60A) is coupled to the control gate node of the CMOS output pulldown driver transistor (Q60) to initiate pulldown of a small sinking current before turn on of the bipolar primary output pulldown transistor (Q44) to reduce the maximum peak output noise (V.sub.OLP).

Abstract: A circuit to be used with bistate and tristate output buffers as a means of diverting from the output pulldown transistor Miller Current arising while the output buffer is powered down. Its purpose is to avoid loading the common bus to which the output buffer is attached, in particular under the circumstances where other output buffers on the bus are causing transitions to occur and the buffer of interest has been powered down. In its preferred embodiment the invention utilizes a MOS transistor coupled between the output pulldown transistor and the lower potential power rail of the output buffer. This MOS transistor is controlled by another MOS transistor coupled to output V.sub.OUT of the buffers. This driver transistor is controlled by the high potential power rail of the buffer and so turns on the Miller Current Discharge Transistor only when the buffer is powered down. The invention also encompasses a discharge transistor coupled to the data input V.sub.

Abstract: In a BiCMOS TTL output buffer circuit, bipolar output pullup and pulldown transistors (Q3,Q4,Q5) source and sink current at an output (V.sub.OUT). A phase splitter transistor (Q2,N4) is coupled to the bipolar output pullup and pulldown transistors for controlling respective conducting states in response to data signals at an input (V.sub.IN) during the active bistate mode of operation. CMOS tristate transistors (P1, ,P2,P4,N2) form a tristate circuit for implementing an inactive tristate mode at the output V.sub.OUT in response to tristate enable signals at a tristate enable input (OE). In order to reduce quiescent input current (I.sub.CC) power dissipation, an input power switch CMOS transistor (NI,N4,P1A) is coupled in the input current path to the high potential power rail (V.sub.CCI). The control gate node of the input power switch CMOS transistor (N1, ,N4,P1A) is coupled to the input (V.sub.IN) to control sourcing of input current (I.sub.

Abstract: An output buffer circuit (10) delivers output signals of high and low potential levels at an output (V.sub.OUT) in response to data signals at an input (V.sub.IN). The output buffer circuit comprises an input stage (12) coupled between a relatively quiet power supply rail (V.sub.CCQ) and a relatively quiet power ground rail (GNDQ), and an output stage (14) coupled between a relatively noisy power supply rail (V.sub.CCN) and a relatively noisy power ground rail (GNDN). A first coupling resistor (R5) is coupled between the relatively quiet and noisy supply rails (V.sub.CCQ, V.sub.CCN) for reducing V.sub.CC droop in the relatively noisy supply rail (V.sub.CCN) which in turn reduces output step in voltage during transition from low to high potential level (LH) at the output (V.sub.OUT). A second coupling resistor (R5A) is coupled between the relatively quiet and noisy ground rails (GNDQ,GNDN).

Abstract: A circuit for use in connection with tristate output buffers in order to provide concurrently for fast discharge of the output pulldown transistor base and at the same time for building in protection against reverse breakdown in the pulldown transistor. The innovation consists of providing a two discharge paths to ground for the base of the output pullup transistor. A low-capacitance path is activated only while the output buffer is in its active mode. In the preferred embodiment of the invention, this low discharge path consists of two CMOS transistors in series, one of which is controlled by the enable signal input E of the buffer circuit and the other by the data signal input V.sub.IN of the buffer circuit. The other path to ground is available whenever the data signal input V.sub.IN is low, regardless of whether the buffer is in its active or inactive mode.

Abstract: A FAST OE signal circuit generates FAST OE signals of high and low potential levels. A SLOW OE signal circuit generates SLOW OE signals corresponding to FAST OE signals. The SLOW OE signals have the same high or low potential level as the corresponding FAST OE signals and occur a specified time delay after the corresponding FAST OE signals. A tristate output buffer circuit operates in the bistate mode when enabled by high potential level OE signals for transmitting binary data signals, and operates in a high Z tristate mode when disabled by low potential level OE signals. The FAST OE signal circuit and SLOW OE signal circuit ae coupled in parallel to the tristate output buffer circuit for enabling and disabling the tristate output buffer circuit. The FAST and SLOW OE signals in combination skew the enable time relative to the disable time.

Abstract: The lower output pulldown tristate circuit for a TTL tristate output buffer circuit includes the enable signal invertor buffer having an OE signal input and an OE signal output providing output enable OE signals, and a Miller killer transistor element having collector and emitter nodes coupled between the base node of the TTL tristate output pulldown transistor and the low potential power rail. The base node of an emitter follower transistor element is coupled to the OE signal input and the emitter node provides a DC Miller killer DCMK signal output in phase with the OE signal input. A voltage divider couples the DCMK signal output to the base node of the Miller killer transistor element for discharging the base of the output pulldown transistor in response ot a high potential DCMK signal during the high impedance tristate at the output. The DC Miller killer circuit is applied in a high speed TTL tristate output and multi-bit line driver.