Patents by Inventor Roy RongQing Yu
Roy RongQing Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10796958Abstract: A process and resultant article of manufacture made by such process comprises forming through vias needed to connect a bottom device layer in a bottom silicon wafer to the one in the top device layer in a top silicon wafer comprising a silicon-on-insulator (SOI) wafer. Through vias are disposed in such a way that they extend from the middle of the line (MOL) interconnect of the top wafer to the buried oxide (BOX) layer of the SOI wafer with appropriate insulation provided to isolate them from the SOI device layer.Type: GrantFiled: July 12, 2018Date of Patent: October 6, 2020Assignee: International Business Machines CorporationInventors: Sampath Purushothaman, Roy Rongqing Yu
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Patent number: 10777454Abstract: An article of manufacture is formed by preparing a first silicon-on-insulator (SOI) wafer with first bonding pads at a first top or back-end-of-line (BEOL) surface thereof, preparing a second SOI wafer with second bonding pads at a second BEOL surface thereof, and attaching the first and second SOI wafers by bonding their bonding pads together, thereby producing a sandwiched wafer with first and second bottom or front-end-of-line (FEOL) surfaces facing outward and with first and second BEOL surfaces facing each other near the midline of the sandwiched wafer. The first SOI wafer then is prepared for packaging by first removing the silicon substrate from the first FEOL surface to reveal a buried oxide (BOX) layer, then fabricating interconnects atop the BOX layer and forming input output pads atop the interconnects.Type: GrantFiled: July 9, 2018Date of Patent: September 15, 2020Assignee: International Business Machines CorporationInventors: Sampath Purushothaman, Roy Rongqing Yu
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Patent number: 10651086Abstract: A process includes forming through vias needed to connect a bottom device layer in a bottom silicon wafer to the one in the top device layer in a top silicon wafer including a silicon-on-insulator (SOI) wafer. Through vias are disposed in such a way that they extend from the middle of the line (MOL) interconnect of the top wafer to the buried oxide (BOX) layer of the SOI wafer with appropriate insulation provided to isolate them from the SOI device layer. A resultant article of manufacture is also disclosed.Type: GrantFiled: August 30, 2018Date of Patent: May 12, 2020Assignee: International Business Machines CorporationInventors: Sampath Purushothaman, Roy Rongqing Yu
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Patent number: 9064717Abstract: A three dimensional device stack structure comprises two or more active device and interconnect layers further connected together using through substrate vias. Methods of forming the three dimensional device stack structure comprise alignment, bonding by lamination, thinning and post thinning processing. The via features enable the retention of alignment through the lamination process and any subsequent process steps thus achieving a mechanically more robust stack structure compared to the prior art.Type: GrantFiled: November 9, 2009Date of Patent: June 23, 2015Assignee: International Business Machines CorporationInventors: Sampath Purushothaman, Mary E. Rothwell, Ghavam Ghavami Shahidi, Roy Rongqing Yu
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Patent number: 8968583Abstract: A method for cleaning a dielectric and metal structure within a microelectronic structure uses an oxygen containing plasma treatment, followed by an alcohol treatment, in turn followed by an aqueous organic acid treatment. Another method for cleaning a dielectric and metal structure within a microelectronic structure uses an aqueous surfactant treatment followed by an alcohol treatment and finally followed by an aqueous organic acid treatment. The former method may be used to clean a plasma etch residue from a dual damascene aperture. The second method may be used to clean a chemical mechanical polish planarizing residue from a dual damascene structure. The two methods may be used sequentially, absent any intervening or subsequent sputtering method, to provide a dual damascene structure within a microelectronic structure.Type: GrantFiled: July 25, 2007Date of Patent: March 3, 2015Assignee: International Business Machines CorporationInventors: Mary Beth Rothwell, Roy Rongqing Yu
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Publication number: 20120193752Abstract: A process and resultant article of manufacture made by such process comprises forming through vias needed to connect a bottom device layer in a bottom silicon wafer to the one in the top device layer in a top silicon wafer comprising a silicon-on-insulator (SOI) wafer. Through vias are disposed in such a way that they extend from the middle of the line (MOL) interconnect of the top wafer to the buried oxide (BOX) layer of the SOI wafer with appropriate insulation provided to isolate them from the SOI device layer.Type: ApplicationFiled: January 29, 2011Publication date: August 2, 2012Applicant: International Business Machines CorporationInventors: Sampath Purushothaman, Roy Rongqing Yu
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Patent number: 8093099Abstract: A three dimensional device stack structure comprises two or more active device and interconnect layers further connected together using through substrate vias. Methods of forming the three dimensional device stack structure comprise alignment, bonding by lamination, thinning and post thinning processing. The via features enable the retention of alignment through the lamination process and any subsequent process steps thus achieving a mechanically more robust stack structure compared to the prior art.Type: GrantFiled: April 20, 2010Date of Patent: January 10, 2012Assignee: International Business Machines CorporationInventors: Sampath Purushothaman, Mary E. Rothwell, Ghavam Ghavami Shahidi, Roy Rongqing Yu
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Patent number: 7994639Abstract: A microelectronic structure, and in particular a semiconductor structure, includes a substrate and a dielectric layer located over the substrate. In addition at least one alignment mark is located interposed between the dielectric layer and the substrate. The at least one alignment mark comprises, or preferably consists essentially of, at least one substantially present element having an atomic number at least 5 greater than a highest atomic number substantially present element within materials surrounding the alignment mark Also included within the microelectronic structure is a dual damascene aperture located within the dielectric layer. The dual damascene aperture may be fabricated using, among other methods, a hybrid lithography method that uses direct write lithography and optical lithography, in conjunction with the at least one alignment mark and an electron beam as an alignment beam.Type: GrantFiled: July 31, 2007Date of Patent: August 9, 2011Assignee: International Business Machines CorporationInventors: James J. Bucchignano, Gerald Warren Gibson, Jr., Mary Beth Rothwell, Roy Rongqing Yu
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Patent number: 7855455Abstract: A three dimensional device stack structure comprises two or more active device and interconnect layers further connected together using through substrate vias. Methods of forming the three dimensional device stack structure comprise alignment, bonding by lamination, thinning and post thinning processing. The via features enable the retention of alignment through the lamination process and any subsequent process steps thus achieving a mechanically more robust stack structure compared to the prior art.Type: GrantFiled: September 26, 2008Date of Patent: December 21, 2010Assignee: International Business Machines CorporationInventors: Sampath Purushothaman, Mary E. Rothwell, Ghavam Ghavami Shahidi, Roy Rongqing Yu
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Publication number: 20100200992Abstract: A three dimensional device stack structure comprises two or more active device and interconnect layers further connected together using through substrate vias. Methods of forming the three dimensional device stack structure comprise alignment, bonding by lamination, thinning and post thinning processing. The via features enable the retention of alignment through the lamination process and any subsequent process steps thus achieving a mechanically more robust stack structure compared to the prior art.Type: ApplicationFiled: April 20, 2010Publication date: August 12, 2010Applicant: International Business Machines CorporationInventors: Sampath Purushothaman, Mary E. Rothwell, Ghavam Ghavami Shahidi, Roy Rongqing Yu
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Publication number: 20100078770Abstract: A three dimensional device stack structure comprises two or more active device and interconnect layers further connected together using through substrate vias. Methods of forming the three dimensional device stack structure comprise alignment, bonding by lamination, thinning and post thinning processing. The via features enable the retention of alignment through the lamination process and any subsequent process steps thus achieving a mechanically more robust stack structure compared to the prior art.Type: ApplicationFiled: September 26, 2008Publication date: April 1, 2010Applicant: International Business Machines CorporationInventors: Sampath Purushothaman, Mary E. Rothwell, Ghavam Ghavami Shahidi, Roy Rongqing Yu
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Publication number: 20090032978Abstract: A microelectronic structure, and in particular a semiconductor structure, includes a substrate and a dielectric layer located over the substrate. In addition at least one alignment mark is located interposed between the dielectric layer and the substrate. The at least one alignment mark comprises, or preferably consists essentially of, at least one substantially present element having an atomic number at least 5 greater than a highest atomic number substantially present element within materials surrounding the alignment mark Also included within the microelectronic structure is a dual damascene aperture located within the dielectric layer. The dual damascene aperture may be fabricated using, among other methods, a hybrid lithography method that uses direct write lithography and optical lithography, in conjunction with the at least one alignment mark and an electron beam as an alignment beam.Type: ApplicationFiled: July 31, 2007Publication date: February 5, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James J. Bucchignano, Gerald Warren Gibson, JR., Mary Beth Rothwell, Roy Rongqing Yu
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Publication number: 20090029543Abstract: A method for cleaning a dielectric and metal structure within a microelectronic structure uses an oxygen containing plasma treatment, followed by an alcohol treatment, in turn followed by an aqueous organic acid treatment. Another method for cleaning a dielectric and metal structure within a microelectronic structure uses an aqueous surfactant treatment followed by an alcohol treatment and finally followed by an aqueous organic acid treatment. The former method may be used to clean a plasma etch residue from a dual damascene aperture. The second method may be used to clean a chemical mechanical polish planarizing residue from a dual damascene structure. The two methods may be used sequentially, absent any intervening or subsequent sputtering method, to provide a dual damascene structure within a microelectronic structure.Type: ApplicationFiled: July 25, 2007Publication date: January 29, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mary Beth Rothwell, Roy Rongqing Yu
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Patent number: 7084479Abstract: In a multilevel microelectronic integrated circuit, air comprises permanent line level dielectric and ultra low-K materials are via level dielectric. The air is supplied to line level subsequent to removal of sacrificial material by clean thermal decomposition and assisted diffusion of byproducts through porosities in the IC structure. Optionally, air is also included within porosities in the via level dielectric. By incorporating air to the extent produced in the invention, intralevel and interlevel dielectric values are minimized.Type: GrantFiled: December 8, 2003Date of Patent: August 1, 2006Assignee: International Business Machines CorporationInventors: Shyng-Tsong Chen, Stefanie Ruth Chiras, Matthew Earl Colburn, Timothy Joseph Dalton, Jeffrey Curtis Hedrick, Elbert Emin Huang, Kaushik Arun Kumar, Michael Wayne Lane, Kelly Malone, Chandrasekhar Narayan, Satyanarayana Venkata Nitta, Sampath Purushothaman, Robert Rosenburg, Christy Sensenich Tyberg, Roy RongQing Yu