Abstract: A method is set forth for writing volatile memory cells embodied on an integrated circuit and taking the form of an array of volatile memory cells including a plurality of word lines and a plurality of bit lines. In use, a first write operation is performed on at least one memory cell at a first time. Further, at a second time, a second write operation is performed on at least one memory cell. During use, various voltage relationships may be employed for enhanced programming. Just by way of example, a voltage at a corresponding word line associated with the at least one memory cell during the first write operation is different than that during the second write operation.

Abstract: A plurality of integrated circuit features are provided in the context of an array of memory cells including a plurality of word lines and a plurality of bit lines. Each memory cell includes a floating body or is volatile memory. The aforementioned features may include, among others, an option whereby the foregoing bit lines may be situated below a channel region of corresponding memory cells, etc.

Abstract: A rewriteable nonvolatile memory cell having two bits per cell is described. The memory cell preferably operates by storing charge in a dielectric charge storage layer or in electrically isolated conductive nanocrystals by a channel hot electron injection method. In preferred embodiments the channel region has a corrugated shape, providing additional isolation between the two storage regions. The channel region is deposited and is preferably formed of polycrystalline germanium or silicon-germanium. The memory cell of the present invention can be formed in memory arrays; in preferred embodiments, multiple memory levels are formed stacked above a single substrate.

Abstract: Methods and apparatus are described for dynamically controlling a charge pump system including a plurality of charge pump stages, with each charge pump stage coupled between an input voltage VIN at an input voltage node and an output voltage VOUT at an output voltage node. In particular, the configuration of the charge pump stages may be dynamically controlled during a transition on VOUT from a first voltage to a second voltage to improve the circuit's transient response.

Abstract: An array of transistors includes a plurality of transistors, a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction. Each transistor includes a source, a drain, a channel and a localized charge storage dielectric. A first transistor of the plurality of transistors and a second transistor of the plurality of transistors share a common source/drain. A first localized charge storage dielectric of the first transistor does not overlap the common source/drain and a second localized charge storage dielectric of the second transistor overlaps the common source/drain.

Abstract: A multi-headed word line driver circuit incorporates bent-gate transistors to reduce the pitch otherwise achievable for interfacing to tightly-pitched array lines. In certain exemplary embodiments, a three-dimensional memory array includes multiple memory blocks and array lines traversing horizontally across at least one memory block. Vertical active area stripes are disposed beneath a first memory block, and a respective plurality of bent-gate electrodes intersects each respective active area stripe to define individual source/drain regions. Every other source/drain region is coupled to a bias node for the active area stripe, and remaining source/drain regions are respectively coupled to a respective array line associated with the first memory block, thereby forming a respective first driver transistor for the respective array line.

Abstract: A decoding circuit for non-binary groups of memory line drivers is disclosed. In one embodiment, an integrated circuit is disclosed comprising a binary decoder and circuitry operative to perform a non-binary arithmetic operation, wherein a result of the non-binary arithmetic operation is provided as input to the binary decoder. In another embodiment, an integrated circuit is disclosed comprising a memory array comprising a plurality of array lines, a non-integral-power-of-two number of array line driver circuits, and control circuitry configured to select one of the array line driver circuits. The control circuitry can comprise a binary decoder and a pre-decoder portion that performs a non-binary arithmetic operation. The concepts described herein may be used alone or in combination.

Abstract: An integrated circuit having a three-dimensional memory array provides for a given number of memory planes, but may be fabricated instead to include a lesser number of memory planes by omitting the masks and processing steps associated with the omitted memory planes, without changing any of the other fabrication masks for the other memory planes or for the remainder of the device, and without requiring routing or other configuration changes to the read or read/write path for the array. Control circuitry for selectively enabling certain layer selector circuits is configurable, and the layer selector circuits are suitably arranged, to couple a respective array line on an implemented memory layer to each respective I/O bus line irrespective of the number of implemented memory planes.

Abstract: An integrated circuit memory array includes alternating first and second types of memory blocks, each memory block including respective array lines shared with a respective array line in an adjacent memory block. The array lines of a defective block of one type are mapped into a spare block of the same type. The array lines of a first adjacent block which are shared with array lines of the defective block, and the array lines of a second adjacent block which are shared with array lines of the defective block, are mapped into a second spare block of the other type, thereby mapping the defective block and portions of both adjacent blocks into just two spare blocks.

Abstract: A memory array having memory cells comprising a diode and a phase change material is reliably programmed by maintaining all unselected memory cells in a reverse biased state. Thus leakage is low and assurance is high that no unselected memory cells are disturbed. In order to avoid disturbing unselected memory cells during sequential writing, previously selected word and bit lines are brought to their unselected voltages before new bit lines and word lines are selected. A modified current mirror structure controls state switching of the phase change material.

Abstract: The invention provides for a nonvolatile memory cell comprising a heater layer in series with a phase change material, such as a chalcogenide. Phase change is achieved in chalcogenide memories by thermal means. Concentrating thermal energy in a relatively small volume assists this phase change. In the present invention, a layer in a pillar-shaped section of a memory cell is etched laterally, decreasing its cross-section. In this way the cross section of the contact area between the heater layer and the phase change material is reduced. In preferred embodiments, the laterally etched layer is the heater layer or a sacrificial layer. In a preferred embodiment, such a cell can be used in a monolithic three dimensional memory array.

Abstract: The invention provides for a write-once nonvolatile memory array, the memory cells comprising a phase change material, such as a chalcogenide. Phase change is achieved in chalcogenide memories by thermal means. The initial, unprogrammed state of each memory cell is a crystalline, low-resistance state, while the programmed state is an amorphous, high-resistance state. Optimizing the circuitry for a write-only memory array, the wordlines or bitlines can be long, with at least 256 cells on a wordline or bitline, and in some embodiments, having thousands of cells on a wordline or bitline. In a preferred embodiment, such an array can be a monolithic three dimensional memory array comprising stacked memory levels.

Abstract: A monolithic integrated circuit includes a memory array having first and second groups of NAND strings, each NAND string comprising at least two series-connected devices and coupled at one end to an associated global array line. NAND strings of the first and second groups differ in at least one physical characteristic, such as the number of series-connected devices forming the NAND string, but both groups are disposed in a region of the memory array traversed by a plurality of global array lines. The memory array may include a three-dimensional memory array having more than one memory plane. Some of the NAND strings of the first group may be disposed on one memory plane, and some of the NAND strings of the second group may be disposed on another memory plane. In some cases, NAND strings of both groups may share global array lines.

Abstract: In an embodiment of the invention an integrated circuit includes a memory array having a first plurality of decoded lines traversing across the memory array and a pair of dual-mode decoders, each decoder coupled to each of the plurality of decoded lines a respective location along said decoded lines, such as at opposite ends thereof. Both decoder circuits receive like address information. Normally both decoder circuits operate in a forward decode mode to decode the address information and drive a selected one of the decoded lines. During a test mode, one decoder is enabled in a reverse decode mode while the other decoder remains in a forward decode mode to verify proper decode operation and integrity of the decoded lines between the decoders.

Abstract: An apparatus is disclosed comprising a plurality of word lines and word line drivers, a plurality of bit lines and bit line drivers, and a plurality of memory cells coupled between respective word lines and bit lines. The apparatus also comprises circuitry operative to select a writing and/or reading condition to apply to a memory cell based on the memory cell's location with respect to one or both of a word line driver and a bit line driver. The apparatus can also comprise circuitry that is operative to select a number of memory cells to be programmed in parallel based on memory cell location with respect to a word line and/or bit line driver.

Abstract: A method of programming a monolithic three-dimensional (3-D) memory having a plurality of levels of memory cells above a silicon substrate is disclosed. The method includes initializing a program voltage and program time interval; selecting a memory cell to be programmed within the three-dimensional memory having the plurality of levels of memory cells; applying a pulse having the program voltage and the program time interval to the selected memory cell; performing a read after write operation with respect to the selected memory cell to determine a measured threshold voltage value; and comparing the measured threshold voltage value to a minimum program voltage. In response to the comparison between the measured threshold voltage value and the minimum program voltage, the method further includes selectively applying at least one subsequent program pulse to the selected memory cell.

Abstract: A semiconductor device comprises two transistors where a gate electrode of one transistor and source or drain of another transistor are located in the same rail. A monolithic three dimensional array contains a plurality of such devices. The transistors in different levels of the array preferably have a different orientation.

Abstract: A three-dimensional (3D) passive element memory cell array provides short word lines while still maintaining a small support circuit area for efficiency. Short, low resistance word line segments on two or more word line layers are connected together in parallel to form a given word line without use of segment switch devices between the word line segments. A shared vertical connection preferably connects the word line segments together and connects to a word line driver circuit disposed generally below the array near the word line. Each word line driver circuit preferably couples its word line either to an associated one of a plurality of selected bias lines or to an unselected bias line associated with the driver circuit, which selected bias lines are themselves decoded to provide for an efficient multi-headed word line decoder.

Abstract: A three-dimensional (3D) passive element memory cell array provides short word lines while still maintaining a small support circuit area for efficiency. Short, low resistance word line segments on two or more word line layers are connected together in parallel to form a given word line without use of segment switch devices between the word line segments. A shared vertical connection preferably connects the word line segments together and connects to a word line driver circuit disposed generally below the array near the word line. Each word line driver circuit preferably couples its word line either to an associated one of a plurality of selected bias lines or to an unselected bias line associated with the driver circuit, which selected bias lines are themselves decoded to provide for an efficient multi-headed word line decoder.

Abstract: A three-dimensional (3D) passive element memory cell array provides short word lines while still maintaining a small support circuit area for efficiency. Short, low resistance word line segments on two or more word line layers are connected together in parallel to form a given word line without use of segment switch devices between the word line segments. A shared vertical connection preferably connects the word line segments together and connects to a word line driver circuit disposed generally below the array near the word line. Each word line driver circuit preferably couples its word line either to an associated one of a plurality of selected bias lines or to an unselected bias line associated with the driver circuit, which selected bias lines are themselves decoded to provide for an efficient multi-headed word line decoder.