Patents by Inventor Roy Stuart Moore
Roy Stuart Moore has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7288723Abstract: A circuit board including a signal transmission channel includes a dielectric substrate and a signal transmission channel which may be formed on the dielectric substrate. The signal transmission channel may include a conductor, a lossy dielectric material which may longitudinally encapsulate the conductor and a conductive material which may longitudinally encapsulate the lossy dielectric.Type: GrantFiled: April 2, 2003Date of Patent: October 30, 2007Assignee: Sun Microsystems, Inc.Inventors: Edward Hugh Welbon, Roy Stuart Moore
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Patent number: 7131047Abstract: A test system includes a device under test and a test circuit board. The device under test includes a plurality of contacts configured to provide output signals. The test circuit board may convey the output signals from the device under test to an analyzer. The test circuit board may include a dielectric layer, a via extending through the dielectric layer, a conductor formed on the dielectric layer and a resistive annular ring having a predetermined resistance value. The resistive annular ring may be formed around the via and may be electrically coupled between the via and the conductor.Type: GrantFiled: April 7, 2003Date of Patent: October 31, 2006Assignee: Sun Microsystems, Inc.Inventors: Edward Hugh Welbon, Roy Stuart Moore
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Patent number: 7080305Abstract: A system and method for correcting data errors. A system for correcting errors in blocks of data received over a communication medium includes an error history unit coupled to an error correction unit. The error history unit may maintain information associated with each bit position of the blocks of data in which a correctable error has occurred. The error correction unit may perform an error correction on a given block of data using an error correction code capable of correcting at least a single bit error and detecting multiple bit errors. Further, in response to detecting a multiple bit error, the error correction unit may correct subsequent errors in the given block of data dependent upon the information maintained by the error history unit.Type: GrantFiled: December 23, 2002Date of Patent: July 18, 2006Assignee: Sun Microsystems, Inc.Inventors: Edward Hugh Welbon, Mary Ellen Mosher, Roy Stuart Moore
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Publication number: 20040196112Abstract: A circuit board including a signal transmission channel includes a dielectric substrate and a signal transmission channel which may be formed on the dielectric substrate. The signal transmission channel may include a conductor, a lossy dielectric material which may longitudinally encapsulate the conductor and a conductive material which may longitudinally encapsulate the lossy dielectric.Type: ApplicationFiled: April 2, 2003Publication date: October 7, 2004Applicant: Sun Microsystems, Inc.Inventors: Edward Hugh Welbon, Roy Stuart Moore
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Publication number: 20040199844Abstract: A test system includes a device under test and a test circuit board. The device under test includes a plurality of contacts configured to provide output signals. The test circuit board may convey the output signals from the device under test to an analyzer. The test circuit board may include a dielectric layer, a via extending through the dielectric layer, a conductor formed on the dielectric layer and a resistive annular ring having a predetermined resistance value. The resistive annular ring may be formed around the via and may be electrically coupled between the via and the conductor.Type: ApplicationFiled: April 7, 2003Publication date: October 7, 2004Applicant: Sun Microsystems, Inc.Inventors: Edward Hugh Welbon, Roy Stuart Moore
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Publication number: 20040193989Abstract: A test system for testing a device under test which includes a plurality of output signal contacts arranged in a particular footprint pattern. The test system may include a test chip which may have a plurality of input signal contacts for receiving signals conveyed from the device under test. The plurality of input signal contacts may be arranged to symmetrically match the particular footprint pattern. The test chip may further include additional contacts for conveying output signals to be analyzed. In addition, the test system includes a test circuit board including a plurality of through-hole vias that connect the plurality of output signal contacts to the plurality of input signal contacts. Further, the test circuit board may include a plurality of blind vias for conveying the output signals to be analyzed to an analyzer unit.Type: ApplicationFiled: March 28, 2003Publication date: September 30, 2004Applicant: Sun Microsystems, Inc.Inventors: Edward Hugh Welbon, Roy Stuart Moore
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Publication number: 20040123213Abstract: A system and method for correcting data errors. A system for correcting errors in blocks of data received over a communication medium includes an error history unit coupled to an error correction unit. The error history unit may maintain information associated with each bit position of the blocks of data in which a correctable error has occurred. The error correction unit may perform an error correction on a given block of data using an error correction code capable of correcting at least a single bit error and detecting multiple bit errors. Further, in response to detecting a multiple bit error, the error correction unit may correct subsequent errors in the given block of data dependent upon the information maintained by the error history unit.Type: ApplicationFiled: December 23, 2002Publication date: June 24, 2004Inventors: Edward Hugh Welbon, Mary Ellen Mosher, Roy Stuart Moore
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Patent number: 6282600Abstract: A method and implementing system are provided in which a service processor is implemented in addition to system processors. The service processor is enabled to access system on-chip registers to acquire system data through the use of the system JTAG bus connections. In one embodiment, logic is provided to determine concurrent calls for use of the same registers by both the system processor(s) and also by the service processor through the JTAG bus. In case of concurrent requests, the JTAG data are held so as not to interfere with system operations until the system processor's use of the registers has been completed.Type: GrantFiled: August 14, 1998Date of Patent: August 28, 2001Assignee: International Business Machines CorporationInventors: Warren Edward Maule, Roy Stuart Moore, David W. Victor, Edward Hugh Welbon
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Patent number: 6189072Abstract: A performance monitor implementing a plurality of counters counts several events to provide an instruction fetch bandwidth analysis, a cycles per instruction (CPI) infinite and finite analysis, an operand fetch bandwidth analysis, an instruction parallelism analysis, and a trailing edge analysis. Such analyses are performed on the performance of a data processing system in order that the designer may develop an improved processor architecture.Type: GrantFiled: December 17, 1996Date of Patent: February 13, 2001Assignee: International Business Machines CorporationInventors: Frank Eliot Levine, Roy Stuart Moore, Charles Philip Roth, Edward Hugh Welbon
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Patent number: 6085338Abstract: A performance monitor implementing a plurality of counters counts several events to provide an instruction fetch bandwidth analysis, a cycles per instruction (CPI) infinite and finite analysis, an operand fetch bandwidth analysis, an instruction parallelism analysis, and a trailing edge analysis. Such analyses are performed on the performance of a data processing system in order that the designer may develop an improved processor architecture.Type: GrantFiled: December 17, 1996Date of Patent: July 4, 2000Assignee: International Business Machines CorporationInventors: Frank Eliot Levine, Roy Stuart Moore, Charles Philip Roth, Edward Hugh Welbon
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Patent number: 6067644Abstract: A processor operable for processing an instruction through a plurality of internal stages will produce a result of the processing of the process at each stage or a reason code why the stage was unable to process the instruction. The result or the reason code will then be passed to a subsequent stage, which will attempt to process the instruction. The second stage will forward the reason code when it cannot produce its own result and it is idle. The second stage will create its own reason code when it is not idle but cannot produce a result, and will forward this reason code.Type: GrantFiled: April 15, 1998Date of Patent: May 23, 2000Assignee: International Business Machines CorporationInventors: Frank Eliot Levine, Roy Stuart Moore, Charles Philip Roth, Edward Hugh Welbon
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Patent number: 5961654Abstract: A performance monitor implementing a plurality of counters counts several events to provide an instruction fetch bandwidth analysis, a cycles per instruction (CPI) infinite and finite analysis, an operand fetch bandwidth analysis, an instruction parallelism analysis, and a trailing edge analysis. Such analyses are performed on the performance of a data processing system in order that the designer may develop an improved processor architecture.Type: GrantFiled: December 17, 1996Date of Patent: October 5, 1999Assignee: International Business Machines CorporationInventors: Frank Eliot Levine, Roy Stuart Moore, Charles Philip Roth, Edward Hugh Welbon
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Patent number: 5938760Abstract: A performance monitor implementing a plurality of counters counts several events to provide an instruction fetch bandwidth analysis, a cycles per instruction (CPI) infinite and finite analysis, an operand fetch bandwidth analysis, an instruction parallelism analysis, and a trailing edge analysis. Such analyses are performed on the performance of a data processing system in order that the designer may develop an improved processor architecture.Type: GrantFiled: December 17, 1996Date of Patent: August 17, 1999Assignee: International Business Machines CorporationInventors: Frank Eliot Levine, Roy Stuart Moore, Charles Philip Roth, Edward Hugh Welbon
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Patent number: 5881306Abstract: A performance monitor implementing a plurality of counters counts several events to provide an instruction fetch bandwidth analysis, a cycles per instruction (CPI) infinite and finite analysis, an operand fetch bandwidth analysis, an instruction parallelism analysis, and a trailing edge analysis. Such analyses are performed on the performance of a data processing system in order that the designer may develop an improved processor architecture.Type: GrantFiled: December 17, 1996Date of Patent: March 9, 1999Assignee: International Business Machines CorporationInventors: Frank Eliot Levine, Roy Stuart Moore, Charles Philip Roth, Edward Hugh Welbon
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Patent number: 5802273Abstract: A performance monitor implementing a plurality of counters counts several events to provide an instruction fetch bandwidth analysis, a cycles per instruction (CPI) infinite and finite analysis, an operand fetch bandwidth analysis, an instruction parallelism analysis, and a trailing edge analysis. Such analyses are performed on the performance of a data processing system in order that the designer may develop an improved processor architecture.Type: GrantFiled: December 17, 1996Date of Patent: September 1, 1998Assignee: International Business Machines CorporationInventors: Frank Eliot Levine, Roy Stuart Moore, Charles Philip Roth, Edward Hugh Welbon