Patents by Inventor Roy Tilghman

Roy Tilghman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080045039
    Abstract: A method is provided for making a FET device in which a nitride layer overlies the PFET gate structure, where the nitride layer has a compressive stress with a magnitude greater than about 2.8 GPa. This compressive stress permits improved device performance in the PFET. The nitride layer is deposited using a high-density plasma (HDP) process, wherein the substrate is disposed on an electrode to which a bias power in the range of about 50 W to about 500 W is supplied. The bias power is characterized as high-frequency power (supplied by an RF generator at 13.56 MHz). The FET device may also include NFET gate structures. A blocking layer is deposited over the NFET gate structures so that the nitride layer overlies the blocking layer; after the blocking layer is removed, the nitride layer is not in contact with the NFET gate structures. The nitride layer has a thickness in the range of about 300-2000 ?.
    Type: Application
    Filed: October 17, 2007
    Publication date: February 21, 2008
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, NOVELLUS SYSTEMS, INC.
    Inventors: Richard Conti, Ronald Bourque, Nancy Klymko, Anita Madan, Michael Smits, Roy Tilghman, Kwong Wong, Daewon Yang
  • Publication number: 20080036007
    Abstract: A method is provided for making a FET device in which a nitride layer overlies the PFET gate structure, where the nitride layer has a compressive stress with a magnitude greater than about 2.8 GPa. This compressive stress permits improved device performance in the PFET. The nitride layer is deposited using a high-density plasma (HDP) process, wherein the substrate is disposed on an electrode to which a bias power in the range of about 50 W to about 500 W is supplied. The bias power is characterized as high-frequency power (supplied by an RF generator at 13.56 MHz). The FET device may also include NFET gate structures. A blocking layer is deposited over the NFET gate structures so that the nitride layer overlies the blocking layer; after the blocking layer is removed, the nitride layer is not in contact with the NFET gate structures. The nitride layer has a thickness in the range of about 300-2000 ?.
    Type: Application
    Filed: October 19, 2007
    Publication date: February 14, 2008
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, NOVELLUS SYSTEMS, INC.
    Inventors: Richard Conti, Ronald Bourque, Nancy Klymko, Anita Madan, Michael Smits, Roy Tilghman, Kwong Wong, Daewon Yang
  • Publication number: 20070007548
    Abstract: A method is provided for making a FET device in which a nitride layer overlies the PFET gate structure, where the nitride layer has a compressive stress with a magnitude greater than about 2.8 GPa. This compressive stress permits improved device performance in the PFET. The nitride layer is deposited using a high-density plasma (HDP) process, wherein the substrate is disposed on an electrode to which a bias power in the range of about 50 W to about 500 W is supplied. The bias power is characterized as high-frequency power (supplied by an RF generator at 13.56 MHz). The FET device may also include NFET gate structures. A blocking layer is deposited over the NFET gate structures so that the nitride layer overlies the blocking layer; after the blocking layer is removed, the nitride layer is not in contact with the NFET gate structures. The nitride layer has a thickness in the range of about 300-2000 ?.
    Type: Application
    Filed: July 6, 2005
    Publication date: January 11, 2007
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, NOVELLUS SYSTEMS INC.
    Inventors: Richard Conti, Ronald Bourque, Nancy Klymko, Anita Madan, Michael Smits, Roy Tilghman, Kwong Wong, Daewon Yang