Patents by Inventor Roza Kotlyar
Roza Kotlyar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11922274Abstract: Quantum dot devices with three of more accumulation gates provided over a single row of a quantum dot formation region are disclosed. Each accumulation gate is electrically coupled to a respective doped region. In this manner, multiple single electron transistors (SETs) are provided along the row. Side and/or center screening gates may be used to apply microwave pulses for qubit control and to control electrostatics so that source and drain regions of the multiple SETs with quantum dots formed along the single row of a quantum dot formation region are sufficiently isolated from one another. Such quantum dot devices provide strong spatial localization of the quantum dots, good control over quantum dot interactions and manipulation, good scalability in the number of quantum dots included in the device, and/or design flexibility in making electrical connections to the quantum dot devices to integrate the quantum dot devices in larger computing devices.Type: GrantFiled: May 18, 2021Date of Patent: March 5, 2024Assignee: Intel CorporationInventors: Hubert C. George, James S. Clarke, Ravi Pillarisetty, Brennen Karl Mueller, Stephanie A. Bojarski, Eric M. Henry, Roza Kotlyar, Thomas Francis Watson, Lester Lampert, Samuel Frederick Neyens
-
Patent number: 11677017Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include a (111) silicon substrate, a (111) germanium quantum well layer above the substrate, and a plurality of gates above the quantum well layer. In some embodiments, a quantum dot device may include a silicon substrate, an insulating material above the silicon substrate, a quantum well layer above the insulating material, and a plurality of gates above the quantum well layer.Type: GrantFiled: September 10, 2021Date of Patent: June 13, 2023Assignee: Intel CorporationInventors: Ravi Pillarisetty, Van H. Le, Nicole K. Thomas, Hubert C. George, Jeanette M. Roberts, Payam Amin, Zachary R. Yoscovits, Roman Caudillo, James S. Clarke, Roza Kotlyar, Kanwaljit Singh
-
Publication number: 20230170388Abstract: Techniques and methods related to strained NMOS and PMOS devices without relaxed substrates, systems incorporating such semiconductor devices, and methods therefor may include a semiconductor device that may have both n-type and p-type semiconductor bodies. Both types of semiconductor bodies may be formed from an initially strained semiconductor material such as silicon germanium. A silicon cladding layer may then be provided at least over or on the n-type semiconductor body. In one example, a lower portion of the semiconductor bodies is formed by a Si extension of the wafer or substrate. By one approach, an upper portion of the semiconductor bodies, formed of the strained SiGe, may be formed by blanket depositing the strained SiGe layer on the Si wafer, and then etching through the SiGe layer and into the Si wafer to form the semiconductor bodies or fins with the lower and upper portions.Type: ApplicationFiled: January 11, 2023Publication date: June 1, 2023Inventors: Stephen M. Cea, Roza Kotlyar, Harold W. Kennel, Anand S. Murthy, Glenn A. Glass, Kelin J. Kuhn, Tahir Ghani
-
Publication number: 20230116170Abstract: Gate-all-around integrated circuit structures having high mobility, and methods of fabricating gate-all-around integrated circuit structures having high mobility, are described. For example, an integrated circuit structure includes a silicon nanowire or nanoribbon. An N-type gate stack is around the silicon nanowire or nanoribbon, the N-type gate stack including a compressively stressing gate electrode. A first N-type epitaxial source or drain structure is at a first end of the silicon nanowire or nanoribbon. A second N-type epitaxial source or drain structure is at a second end of the silicon nanowire or nanoribbon. The silicon nanowire or nanoribbon has a <110> plane between the first N-type epitaxial source or drain structure and the second N-type epitaxial source or drain structure.Type: ApplicationFiled: November 28, 2022Publication date: April 13, 2023Inventors: Roza KOTLYAR, Rishabh MEHANDRU, Stephen CEA, Biswajeet GUHA, Dax CRUM, Tahir GHANI
-
Patent number: 11581406Abstract: Techniques and methods related to strained NMOS and PMOS devices without relaxed substrates, systems incorporating such semiconductor devices, and methods therefor may include a semiconductor device that may have both n-type and p-type semiconductor bodies. Both types of semiconductor bodies may be formed from an initially strained semiconductor material such as silicon germanium. A silicon cladding layer may then be provided at least over or on the n-type semiconductor body. In one example, a lower portion of the semiconductor bodies is formed by a Si extension of the wafer or substrate. By one approach, an upper portion of the semiconductor bodies, formed of the strained SiGe, may be formed by blanket depositing the strained SiGe layer on the Si wafer, and then etching through the SiGe layer and into the Si wafer to form the semiconductor bodies or fins with the lower and upper portions.Type: GrantFiled: November 1, 2021Date of Patent: February 14, 2023Assignee: Daedalus Prime LLCInventors: Stephen M. Cea, Roza Kotlyar, Harold W. Kennel, Anand S. Murthy, Glenn A. Glass, Kelin J. Kuhn, Tahir Ghani
-
Patent number: 11538806Abstract: Gate-all-around integrated circuit structures having high mobility, and methods of fabricating gate-all-around integrated circuit structures having high mobility, are described. For example, an integrated circuit structure includes a silicon nanowire or nanoribbon. An N-type gate stack is around the silicon nanowire or nanoribbon, the N-type gate stack including a compressively stressing gate electrode. A first N-type epitaxial source or drain structure is at a first end of the silicon nanowire or nanoribbon. A second N-type epitaxial source or drain structure is at a second end of the silicon nanowire or nanoribbon. The silicon nanowire or nanoribbon has a <110> plane between the first N-type epitaxial source or drain structure and the second N-type epitaxial source or drain structure.Type: GrantFiled: September 27, 2018Date of Patent: December 27, 2022Assignee: Intel CorporationInventors: Roza Kotlyar, Rishabh Mehandru, Stephen Cea, Biswajeet Guha, Dax Crum, Tahir Ghani
-
Patent number: 11387320Abstract: Techniques are disclosed for forming transistor devices having source and drain regions with high concentrations of boron doped germanium. In some embodiments, an in situ boron doped germanium, or alternatively, boron doped silicon germanium capped with a heavily boron doped germanium layer, are provided using selective epitaxial deposition in the source and drain regions and their corresponding tip regions. In some such cases, germanium concentration can be, for example, in excess of 50 atomic % and up to 100 atomic %, and the boron concentration can be, for instance, in excess of 1E20 cm?3. A buffer providing graded germanium and/or boron concentrations can be used to better interface disparate layers. The concentration of boron doped in the germanium at the epi-metal interface effectively lowers parasitic resistance without degrading tip abruptness. The techniques can be embodied, for instance, in planar or non-planar transistor devices.Type: GrantFiled: December 9, 2019Date of Patent: July 12, 2022Assignee: Intel CorporationInventors: Anand S. Murthy, Glenn A. Glass, Tahir Ghani, Ravi Pillarisetty, Niloy Mukherjee, Jack T. Kavalieros, Roza Kotlyar, Willy Rachmady, Mark Y. Liu
-
Patent number: 11367722Abstract: A nanowire transistor structure has a first device region with a first body of semiconductor material having a first cross-sectional shape. A second device region has a second body with a second cross-sectional shape different from the first cross-sectional shape. The first device section is vertically above or below the second device section with the bodies extending horizontally between a source and drain. A first gate structure is wrapped around the first body and a second gate structure is wrapped around the second body. Differences in the geometries of the nanowires can be used to optimize performance in the first device section independently of the second device section.Type: GrantFiled: September 21, 2018Date of Patent: June 21, 2022Assignee: Intel CorporationInventors: Aaron Lilak, Stephen Cea, Gilbert Dewey, Willy Rachmady, Roza Kotlyar, Rishabh Mehandru, Sean Ma, Ehren Mannebach, Anh Phan, Cheng-Ying Huang
-
Publication number: 20220190135Abstract: Disclosed herein are lateral gate material arrangements for quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; and a gate above the quantum well stack, wherein the gate includes a gate electrode, the gate electrode includes a first material proximate to side faces of the gate and a second material proximate to a center of the gate, and the first material has a different material composition than the second material.Type: ApplicationFiled: December 10, 2020Publication date: June 16, 2022Inventors: Roza Kotlyar, Stephanie A. Bojarski, Hubert C. George, Payam Amin, Patrick H. Keys, Ravi Pillarisetty, Roman Caudillo, Florian Luethi, James S. Clarke
-
Publication number: 20220059656Abstract: Techniques and methods related to strained NMOS and PMOS devices without relaxed substrates, systems incorporating such semiconductor devices, and methods therefor may include a semiconductor device that may have both n-type and p-type semiconductor bodies. Both types of semiconductor bodies may be formed from an initially strained semiconductor material such as silicon germanium. A silicon cladding layer may then be provided at least over or on the n-type semiconductor body. In one example, a lower portion of the semiconductor bodies is formed by a Si extension of the wafer or substrate. By one approach, an upper portion of the semiconductor bodies, formed of the strained SiGe, may be formed by blanket depositing the strained SiGe layer on the Si wafer, and then etching through the SiGe layer and into the Si wafer to form the semiconductor bodies or fins with the lower and upper portions.Type: ApplicationFiled: November 1, 2021Publication date: February 24, 2022Inventors: Stephen M. Cea, Roza Kotlyar, Harold W. Kennel, Anand S. Murthy, Glenn A. Glass, Kelin J. Kuhn, Tahir Ghani
-
Publication number: 20220013658Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include a (111) silicon substrate, a (111) germanium quantum well layer above the substrate, and a plurality of gates above the quantum well layer. In some embodiments, a quantum dot device may include a silicon substrate, an insulating material above the silicon substrate, a quantum well layer above the insulating material, and a plurality of gates above the quantum well layer.Type: ApplicationFiled: September 10, 2021Publication date: January 13, 2022Applicant: Intel CorporationInventors: Ravi Pillarisetty, Van H. Le, Nicole K. Thomas, Hubert C. George, Jeanette M. Roberts, Payam Amin, Zachary R. Yoscovits, Roman Caudillo, James S. Clarke, Roza Kotlyar, Kanwaljit Singh
-
Publication number: 20210399119Abstract: Embodiments disclosed herein comprise a high electron mobility transistor (HEMT). In an embodiment, the HEMT comprises a heterojunction channel that includes a first semiconductor layer and a second semiconductor layer over the first semiconductor layer. In an embodiment a first interface layer is between the first semiconductor layer and the second semiconductor layer, and a second interface layer is over the first interface layer. In an embodiment, the HEMT further comprises a source contact, a drain contact, and a gate contact between the source contact and the drain contact.Type: ApplicationFiled: June 23, 2020Publication date: December 23, 2021Inventors: Suresh VISHWANATH, Roza KOTLYAR, Han Wui THEN, Robert EHLERT, Glenn A. GLASS, Anand S. MURTHY, Sandrine CHARUE-BAKKER
-
Patent number: 11195919Abstract: Techniques and methods related to strained NMOS and PMOS devices without relaxed substrates, systems incorporating such semiconductor devices, and methods therefor may include a semiconductor device that may have both n-type and p-type semiconductor bodies. Both types of semiconductor bodies may be formed from an initially strained semiconductor material such as silicon germanium. A silicon cladding layer may then be provided at least over or on the n-type semiconductor body. In one example, a lower portion of the semiconductor bodies is formed by a Si extension of the wafer or substrate. By one approach, an upper portion of the semiconductor bodies, formed of the strained SiGe, may be formed by blanket depositing the strained SiGe layer on the Si wafer, and then etching through the SiGe layer and into the Si wafer to form the semiconductor bodies or fins with the lower and upper portions.Type: GrantFiled: October 1, 2018Date of Patent: December 7, 2021Assignee: Intel CorporationInventors: Stephen M. Cea, Roza Kotlyar, Harold W. Kennel, Anand S. Murthy, Glenn A. Glass, Kelin J. Kuhn, Tahir Ghani
-
Patent number: 11183564Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer and a barrier layer; a first gate metal above the quantum well stack, wherein the barrier layer is between the first gate metal and the quantum well layer; and a second gate metal above the quantum well stack, wherein the barrier layer is between the second gate metal and the quantum well layer, and a material structure of the second gate metal is different from a material structure of the first gate metal.Type: GrantFiled: June 21, 2018Date of Patent: November 23, 2021Assignee: Intel CorporationInventors: Nicole K. Thomas, Ravi Pillarisetty, Payam Amin, Roza Kotlyar, Patrick H. Keys, Hubert C. George, Kanwaljit Singh, James S. Clarke, David J. Michalak, Lester Lampert, Zachary R. Yoscovits, Roman Caudillo, Jeanette M. Roberts
-
Patent number: 11158731Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include a (111) silicon substrate, a (111) germanium quantum well layer above the substrate, and a plurality of gates above the quantum well layer. In some embodiments, a quantum dot device may include a silicon substrate, an insulating material above the silicon substrate, a quantum well layer above the insulating material, and a plurality of gates above the quantum well layer.Type: GrantFiled: September 28, 2017Date of Patent: October 26, 2021Assignee: Intel CorporationInventors: Ravi Pillarisetty, Van H. Le, Nicole K. Thomas, Hubert C. George, Jeanette Roberts, Payam Amin, Zachary R. Yoscovits, Roman Caudillo, James S. Clarke, Roza Kotlyar, Kanwaljit Singh
-
Patent number: 11107891Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack; a plurality of first gates above the quantum well stack; and a plurality of second gates above the quantum well stack; wherein the plurality of first gates are arranged in electrically continuous first rows and the plurality of second gates are arranged in electrically continuous second rows parallel to the first rows. Quantum dot devices according to various embodiments of the present disclosure are based on arranging first and second gates in hexagonal/honeycomb arrays.Type: GrantFiled: December 23, 2017Date of Patent: August 31, 2021Assignee: Intel CorporationInventors: Ravi Pillarisetty, Hubert C. George, Nicole K. Thomas, Jeanette M. Roberts, Roman Caudillo, Zachary R. Yoscovits, Kanwaljit Singh, Roza Kotlyar, Patrick H. Keys, James S. Clarke
-
Patent number: 10868246Abstract: Conductive bridge random access memory (CBRAM) devices with low thermal conductivity electrolyte sublayers are described. In an example, a conductive bridge random access memory (CBRAM) device includes a conductive interconnect disposed in an inter-layer dielectric (ILD) layer disposed above a substrate. The CBRAM device also includes a CBRAM element disposed on the conductive interconnect. The CBRAM element includes an active electrode layer disposed on the conductive interconnect, and a resistance switching layer disposed on the active electrode layer. The resistance switching layer includes a first electrolyte material layer disposed on a second electrolyte material layer, the second electrolyte material layer disposed on the active electrode layer and having a thermal conductivity lower than a thermal conductivity of the first electrolyte material layer. A passive electrode layer is disposed on the first electrolyte material of the resistance switching layer.Type: GrantFiled: September 30, 2016Date of Patent: December 15, 2020Assignee: Intel CorporationInventors: Elijah V. Karpov, Roza Kotlyar, Prashant Majhi, Jeffery D. Bielefeld
-
Publication number: 20200381549Abstract: Techniques are disclosed for incorporating high mobility strained channels into fin-based NMOS transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, a germanium or silicon germanium film is cladded onto silicon fins in order to provide a desired tensile strain in the core of the fin, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and cladding deposition can occur at a plurality of locations within typical process flow. In various embodiments, fins may be formed with a minimum width (or later thinned) so as to improve transistor performance. In some embodiments, a thinned fin also increases tensile strain across the core of a cladded fin. In some cases, strain in the core may be further enhanced by adding an embedded silicon epitaxial source and drain.Type: ApplicationFiled: August 20, 2020Publication date: December 3, 2020Applicant: INTEL CORPORATIONInventors: STEPHEN M. CEA, ROZA KOTLYAR, HAROLD W. KENNEL, GLENN A. GLASS, ANAND S. MURTHY, WILLY RACHMADY, TAHIR GHANI
-
Patent number: 10854752Abstract: Techniques are disclosed for incorporating high mobility strained channels into fin-based NMOS transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, a germanium or silicon germanium film is cladded onto silicon fins in order to provide a desired tensile strain in the core of the fin, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and cladding deposition can occur at a plurality of locations within typical process flow. In various embodiments, fins may be formed with a minimum width (or later thinned) so as to improve transistor performance. In some embodiments, a thinned fin also increases tensile strain across the core of a cladded fin. In some cases, strain in the core may be further enhanced by adding an embedded silicon epitaxial source and drain.Type: GrantFiled: December 10, 2018Date of Patent: December 1, 2020Assignee: Intel CorporationInventors: Stephen M. Cea, Roza Kotlyar, Harold W. Kennel, Glenn A. Glass, Anand S. Murthy, Willy Rachmady, Tahir Ghani
-
Publication number: 20200350423Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include a (111) silicon substrate, a (111) germanium quantum well layer above the substrate, and a plurality of gates above the quantum well layer. In some embodiments, a quantum dot device may include a silicon substrate, an insulating material above the silicon substrate, a quantum well layer above the insulating material, and a plurality of gates above the quantum well layer.Type: ApplicationFiled: September 28, 2017Publication date: November 5, 2020Applicant: Intel CorporationInventors: Ravi Pillarisetty, Van H. Le, Nicole K. Thomas, Hubert C. George, Jeanette Roberts, Payam Amin, Zachary R. Yoscovits, Roman Caudillo, James S. Clarke, Roza Kotlyar, Kanwaljit Singh