Patents by Inventor Ru Feng Du
Ru Feng Du has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240056046Abstract: An audio amplifier includes: a buck controller configured to control an output voltage at a first supply terminal, the output voltage selected from a set including a plurality of output voltages, where the output voltage takes a settling time to settle; a first audio bridge including: a class-AB driver stage coupled to the first supply terminal, and a delay insertion circuit configured to receive a processed digital stream and provide the processed digital stream to the class-AB driver stage a delay time after receiving the processed digital stream, where the delay time is based on the settling time; and an audio amplitude detector configured to detect a first peak amplitude in the first digital audio stream, where the buck controller is configured to select a lowest output voltage from the set that is higher than the first peak amplitude plus a headroom voltage.Type: ApplicationFiled: October 24, 2023Publication date: February 15, 2024Inventors: XiangSheng Li, Ru Feng Du
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Patent number: 11831286Abstract: An audio amplifier includes: a buck controller configured to control an output voltage at a first supply terminal, the output voltage selected from a set including a plurality of output voltages, where the output voltage takes a settling time to settle; a first audio bridge including: a class-AB driver stage coupled to the first supply terminal, and a delay insertion circuit configured to receive a processed digital stream and provide the processed digital stream to the class-AB driver stage a delay time after receiving the processed digital stream, where the delay time is based on the settling time; and an audio amplitude detector configured to detect a first peak amplitude in the first digital audio stream, where the buck controller is configured to select a lowest output voltage from the set that is higher than the first peak amplitude plus a headroom voltage.Type: GrantFiled: April 27, 2021Date of Patent: November 28, 2023Assignee: STMicroelectronics (Shenzhen) R&D Co. Ltd.Inventors: XiangSheng Li, Ru Feng Du
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Patent number: 11750163Abstract: In an embodiment, a class-D amplifier includes an input terminal configured to receive an input signal; a comparator having an input coupled to the input terminal; a deglitching circuit having an input coupled to an output of the comparator; and a driving circuit having an input coupled to an output of the deglitching circuit. The deglitching circuit includes a logic circuit coupled between the input of the deglitching circuit and the output of the deglitching circuit. The logic circuit is configured to receive a clock signal having the same frequency as the switching frequency of the class-D amplifier.Type: GrantFiled: March 12, 2021Date of Patent: September 5, 2023Assignee: STMicroelectronics (Shenzhen) R&D Co. Ltd.Inventors: Ru Feng Du, Qi Yu Liu
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Publication number: 20210250010Abstract: An audio amplifier includes: a buck controller configured to control an output voltage at a first supply terminal, the output voltage selected from a set including a plurality of output voltages, where the output voltage takes a settling time to settle; a first audio bridge including: a class-AB driver stage coupled to the first supply terminal, and a delay insertion circuit configured to receive a processed digital stream and provide the processed digital stream to the class-AB driver stage a delay time after receiving the processed digital stream, where the delay time is based on the settling time; and an audio amplitude detector configured to detect a first peak amplitude in the first digital audio stream, where the buck controller is configured to select a lowest output voltage from the set that is higher than the first peak amplitude plus a headroom voltage.Type: ApplicationFiled: April 27, 2021Publication date: August 12, 2021Inventors: XiangSheng Li, Ru Feng Du
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Publication number: 20210203293Abstract: In an embodiment, a class-D amplifier includes an input terminal configured to receive an input signal; a comparator having an input coupled to the input terminal; a deglitching circuit having an input coupled to an output of the comparator; and a driving circuit having an input coupled to an output of the deglitching circuit. The deglitching circuit includes a logic circuit coupled between the input of the deglitching circuit and the output of the deglitching circuit. The logic circuit is configured to receive a clock signal having the same frequency as the switching frequency of the class-D amplifier.Type: ApplicationFiled: March 12, 2021Publication date: July 1, 2021Inventors: Ru Feng Du, Qi Yu Liu
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Patent number: 11018644Abstract: An audio amplifier includes: a buck controller configured to control an output voltage at a first supply terminal, the output voltage selected from a set including a plurality of output voltages, where the output voltage takes a settling time to settle; a first audio bridge including: a class-AB driver stage coupled to the first supply terminal, and a delay insertion circuit configured to receive a processed digital stream and provide the processed digital stream to the class-AB driver stage a delay time after receiving the processed digital stream, where the delay time is based on the settling time; and an audio amplitude detector configured to detect a first peak amplitude in the first digital audio stream, where the buck controller is configured to select a lowest output voltage from the set that is higher than the first peak amplitude plus a headroom voltage.Type: GrantFiled: November 25, 2019Date of Patent: May 25, 2021Assignee: STMicroelectronics (Shenzen) R&D Co. Ltd.Inventors: XiangSheng Li, Ru Feng Du
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Patent number: 10965263Abstract: In an embodiment, a class-D amplifier includes an input terminal configured to receive an input signal; a comparator having an input coupled to the input terminal; a deglitching circuit having an input coupled to an output of the comparator; and a driving circuit having an input coupled to an output of the deglitching circuit. The deglitching circuit includes a logic circuit coupled between the input of the deglitching circuit and the output of the deglitching circuit. The logic circuit is configured to receive a clock signal having the same frequency as the switching frequency of the class-D amplifier.Type: GrantFiled: March 15, 2019Date of Patent: March 30, 2021Assignee: STMICROELECTRONICS (SHENZHEN) R&D CO. LTD.Inventors: Ru Feng Du, Qi Yu Liu
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Patent number: 10944366Abstract: In an embodiment, a class-AB amplifier includes: an output stage that includes a pair of half-bridges configured to be coupled to a load; and a current sensing circuit coupled to a first half-bridge of the pair of half-bridges. The current sensing circuit includes a resistive element and is configured to sense a load current flowing through the load by: mirroring a current flowing through a first transistor of the first half-bridge to generate a mirrored current, flowing the mirrored current through the resistive element, and sensing the load current based on a voltage of the resistive element.Type: GrantFiled: March 4, 2019Date of Patent: March 9, 2021Assignee: STMICROELECTRONICS (SHENZHEN) R&D CO. LTDInventors: Ru Feng Du, XiangSheng Li
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Publication number: 20200295723Abstract: In an embodiment, a class-D amplifier includes an input terminal configured to receive an input signal; a comparator having an input coupled to the input terminal; a deglitching circuit having an input coupled to an output of the comparator; and a driving circuit having an input coupled to an output of the deglitching circuit. The deglitching circuit includes a logic circuit coupled between the input of the deglitching circuit and the output of the deglitching circuit. The logic circuit is configured to receive a clock signal having the same frequency as the switching frequency of the class-D amplifier.Type: ApplicationFiled: March 15, 2019Publication date: September 17, 2020Inventors: Ru Feng Du, Qi Yu Liu
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Publication number: 20200287507Abstract: In an embodiment, a class-AB amplifier includes: an output stage that includes a pair of half-bridges configured to be coupled to a load; and a current sensing circuit coupled to a first half-bridge of the pair of half-bridges. The current sensing circuit includes a resistive element and is configured to sense a load current flowing through the load by: mirroring a current flowing through a first transistor of the first half-bridge to generate a mirrored current, flowing the mirrored current through the resistive element, and sensing the load current based on a voltage of the resistive element.Type: ApplicationFiled: March 4, 2019Publication date: September 10, 2020Inventors: Ru Feng Du, XiangSheng Li
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Publication number: 20200169234Abstract: An audio amplifier includes: a buck controller configured to control an output voltage at a first supply terminal, the output voltage selected from a set including a plurality of output voltages, where the output voltage takes a settling time to settle; a first audio bridge including: a class-AB driver stage coupled to the first supply terminal, and a delay insertion circuit configured to receive a processed digital stream and provide the processed digital stream to the class-AB driver stage a delay time after receiving the processed digital stream, where the delay time is based on the settling time; and an audio amplitude detector configured to detect a first peak amplitude in the first digital audio stream, where the buck controller is configured to select a lowest output voltage from the set that is higher than the first peak amplitude plus a headroom voltage.Type: ApplicationFiled: November 25, 2019Publication date: May 28, 2020Inventors: XiangSheng Li, Ru Feng Du
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Patent number: 10530309Abstract: A class D amplifier receives and amplifies a differential analog signal which is then differentially integrated. Two pulse width modulators generate pulse signals corresponding to the differentially integrated analog signal and two power units generate output pulse signals. The outputs the power units are coupled to input terminals of integrators via a resistor feedback network. An analog output unit converts the pulse signals to an output analog signal. The differential integration circuitry implements a soft transition between mute/un-mute. In mute, the integrator output is fixed. During the soft transition, the PWM outputs change slowly from a fixed 50% duty cycle to a final value to ensure that no pop noise is present in the output as a result of mode change.Type: GrantFiled: December 17, 2018Date of Patent: January 7, 2020Assignee: STMicroelectronics (Shenzhen) R&D Co. LtdInventors: Ru Feng Du, Qi Yu Liu
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Publication number: 20190123694Abstract: A class D amplifier receives and amplifies a differential analog signal which is then differentially integrated. Two pulse width modulators generate pulse signals corresponding to the differentially integrated analog signal and two power units generate output pulse signals. The outputs the power units are coupled to input terminals of integrators via a resistor feedback network. An analog output unit converts the pulse signals to an output analog signal. The differential integration circuitry implements a soft transition between mute/un-mute. In mute, the integrator output is fixed. During the soft transition, the PWM outputs change slowly from a fixed 50% duty cycle to a final value to ensure that no pop noise is present in the output as a result of mode change.Type: ApplicationFiled: December 17, 2018Publication date: April 25, 2019Applicant: STMicroelectronics (Shenzhen) R&D Co. LtdInventors: Ru Feng DU, Qi Yu LIU
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Patent number: 10193506Abstract: A class D amplifier receives and amplifies a differential analog signal which is then differentially integrated. Two pulse width modulators generate pulse signals corresponding to the differentially integrated analog signal and two power units generate output pulse signals. The outputs the power units are coupled to input terminals of integrators via a resistor feedback network. An analog output unit converts the pulse signals to an output analog signal. The differential integration circuitry implements a soft transition between mute/un-mute. In mute, the integrator output is fixed. During the soft transition, the PWM outputs change slowly from a fixed 50% duty cycle to a final value to ensure that no pop noise is present in the output as a result of mode change.Type: GrantFiled: December 13, 2016Date of Patent: January 29, 2019Assignee: STMicroelectronics (Shenzhen) R&D Co. LtdInventors: Ru Feng Du, Qi Yu Liu
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Patent number: 9667201Abstract: A class-D audio amplifier incorporates an overcurrent protection scheme implementing two overcurrent thresholds to avoid a dynamic impedance drop. When output current reaches the first threshold as a result of an impedance drop across the speaker, the overcurrent protection circuitry limits the output current to the value of the first threshold, but does not shut down the circuit. The second threshold is used to detect an overcurrent condition to shut down the circuit. Current limiting logic of a first channel monitors the overcurrent condition of a second channel and controls the first channel output in response thereto. This permits the second channel output current to reach the second threshold if the circuit is experiencing a short-circuit condition. This scheme also allows the output current to drop below the first threshold if the overcurrent condition of the second channel is caused by an impedance drop across the output speaker.Type: GrantFiled: January 21, 2016Date of Patent: May 30, 2017Assignee: STMicroelectronics (Shenzhen) R&D Co. LtdInventors: Ru Feng Du, Qi Yu Liu
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Publication number: 20170093348Abstract: A class D amplifier receives and amplifies a differential analog signal which is then differentially integrated. Two pulse width modulators generate pulse signals corresponding to the differentially integrated analog signal and two power units generate output pulse signals. The outputs the power units are coupled to input terminals of integrators via a resistor feedback network. An analog output unit converts the pulse signals to an output analog signal. The differential integration circuitry implements a soft transition between mute/un-mute. In mute, the integrator output is fixed. During the soft transition, the PWM outputs change slowly from a fixed 50% duty cycle to a final value to ensure that no pop noise is present in the output as a result of mode change.Type: ApplicationFiled: December 13, 2016Publication date: March 30, 2017Applicant: STMicroelectronics (Shenzhen) R&D Co. LtdInventors: Ru Feng Du, Qi Yu Liu
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Patent number: 9577579Abstract: A class D amplifier receives and amplifies a differential analog signal which is then differentially integrated. Two pulse width modulators generate pulse signals corresponding to the differentially integrated analog signal and two power units generate output pulse signals. The outputs the power units are coupled to input terminals of integrators via a resistor feedback network. An analog output unit converts the pulse signals to an output analog signal. The differential integration circuitry implements a soft transition between mute/un-mute. In mute, the integrator output is fixed. During the soft transition, the PWM outputs change slowly from a fixed 50% duty cycle to a final value to ensure that no pop noise is present in the output as a result of mode change.Type: GrantFiled: March 1, 2016Date of Patent: February 21, 2017Assignee: STMicroelectronics (Shenzhen) R&D Co. LtdInventors: Ru Feng Du, Qi Yu Liu
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Publication number: 20160181988Abstract: A class D amplifier receives and amplifies a differential analog signal which is then differentially integrated. Two pulse width modulators generate pulse signals corresponding to the differentially integrated analog signal and two power units generate output pulse signals. The outputs the power units are coupled to input terminals of integrators via a resistor feedback network. An analog output unit converts the pulse signals to an output analog signal. The differential integration circuitry implements a soft transition between mute/un-mute. In mute, the integrator output is fixed. During the soft transition, the PWM outputs change slowly from a fixed 50% duty cycle to a final value to ensure that no pop noise is present in the output as a result of mode change.Type: ApplicationFiled: March 1, 2016Publication date: June 23, 2016Applicant: STMicroelectronics (Shenzhen) R&D Co. LtdInventors: Ru Feng Du, Qi Yu Liu
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Publication number: 20160142024Abstract: A class-D audio amplifier incorporates an overcurrent protection scheme implementing two overcurrent thresholds to avoid a dynamic impedance drop. When output current reaches the first threshold as a result of an impedance drop across the speaker, the overcurrent protection circuitry limits the output current to the value of the first threshold, but does not shut down the circuit. The second threshold is used to detect an overcurrent condition to shut down the circuit. Current limiting logic of a first channel monitors the overcurrent condition of a second channel and controls the first channel output in response thereto. This permits the second channel output current to reach the second threshold if the circuit is experiencing a short-circuit condition. This scheme also allows the output current to drop below the first threshold if the overcurrent condition of the second channel is caused by an impedance drop across the output speaker.Type: ApplicationFiled: January 21, 2016Publication date: May 19, 2016Applicant: STMicroelectronics (Shenzhen) R&D Co. LtdInventors: Ru Feng Du, Qi Yu Liu
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Patent number: 9306523Abstract: A class D amplifier receives and amplifies a differential analog signal which is then differentially integrated. Two pulse width modulators generate pulse signals corresponding to the differentially integrated analog signal and two power units generate output pulse signals. The outputs the power units are coupled to input terminals of integrators via a resistor feedback network. An analog output unit converts the pulse signals to an output analog signal. The differential integration circuitry implements a soft transition between mute/un-mute. In mute, the integrator output is fixed. During the soft transition, the PWM outputs change slowly from a fixed 50% duty cycle to a final value to ensure that no pop noise is present in the output as a result of mode change.Type: GrantFiled: September 5, 2014Date of Patent: April 5, 2016Assignee: STMicroelectronics (Shenzhen) R&D Co. LtdInventors: Ru Feng Du, Qi Yu Liu