Patents by Inventor Ru-Gun Liu
Ru-Gun Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11415890Abstract: A method for mask data synthesis and mask making includes calibrating an optical proximity correction (OPC) model by adjusting a plurality of parameters including a first parameter and a second parameter, wherein the first parameter indicates a long-range effect caused by an electron-beam lithography tool for making a mask used to manufacture a structure, and the second parameter indicates a geometric feature of a structure or a manufacturing process to make the structure, generating a device layout, calculating a first grid pattern density map of the device layout, generating a long-range correction map, at least based on the calibrated OPC model and the first grid pattern density map of the device layout, and performing an OPC to generate a corrected mask layout, at least based on the generated long-range correction map and the calibrated OPC model.Type: GrantFiled: March 8, 2021Date of Patent: August 16, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsu-Ting Huang, Shih-Hsiang Lo, Ru-Gun Liu
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Patent number: 11392742Abstract: Implementations of the present disclosure provide coloring methods that sort and pre-color nodes of G0-linked networks in a multiple-patterning technology (MPT)-compliant layout design by coordinate. In one embodiment, a method includes identifying target networks in a circuit layout, each target network having two or more linked nodes representing circuit patterns, and each target network being presented in an imaginary X-Y coordinate plane, assigning a first feature to a first node in each target network, the first node is determined using a coordinate-based method, and assigning the first feature and a second feature to remaining nodes in each target network in an alternating manner so that any two immediately adjacent linked nodes in each target network have different features.Type: GrantFiled: October 5, 2020Date of Patent: July 19, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Ping Chiang, Ming-Hui Chih, Chih-Wei Hsu, Ping-Chieh Wu, Ya-Ting Chang, Tsung-Yu Wang, Wen-Li Cheng, Hui En Yin, Wen-Chun Huang, Ru-Gun Liu, Tsai-Sheng Gau
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Publication number: 20220223474Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate, a first conductive feature embedded in a top portion of the substrate, a dielectric layer over the substrate, and a second conductive feature surrounded by the dielectric layer and in contact with the first conductive feature. The first conductive feature includes a metal layer and a reflective layer on the metal layer. The reflective layer has a reflectivity higher than the metal layer.Type: ApplicationFiled: March 28, 2022Publication date: July 14, 2022Inventors: Ru-Gun Liu, Shih-Ming Chang, Hoi-Tou Ng
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Patent number: 11387113Abstract: A method includes forming a material layer over a substrate, forming a first hard mask (HM) layer over the material layer, forming a first trench, along a first direction, in the first HM layer. The method also includes forming first spacers along sidewalls of the first trench, forming a second trench in the first HM layer parallel to the first trench, by using the first spacers to guard the first trench. The method also includes etching the material layer through the first trench and the second trench, removing the first HM layer and the first spacers, forming a second HM layer over the material layer, forming a third trench in the second HM layer. The third trench extends along a second direction that is perpendicular to the first direction and overlaps with the first trench. The method also includes etching the material layer through the third trench.Type: GrantFiled: October 26, 2020Date of Patent: July 12, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yung-Sung Yen, Chung-Ju Lee, Chun-Kuang Chen, Chia-Tien Wu, Ta-Ching Yu, Kuei-Shun Chen, Ru-Gun Liu, Shau-Lin Shue, Tsai-Sheng Gau, Yung-Hsu Wu
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Patent number: 11360379Abstract: A method for manufacturing a photo mask for a semiconductor device includes receiving a plurality of hotspot regions of a mask layout corresponding to the semiconductor device. The method further includes classifying the plurality of hotspot regions into two or more hotspot groups such that same or similar hotspot regions are classified into same hotspot groups. The hotspot groups includes a first hotspot group that has at least two hotspot regions. The method also includes correcting a first hotspot region of the first hotspot group to generate an enhancement of the first hotspot region and correcting other hotspot regions of the first hotspot group using the enhancement of the first hotspot region to generate enhancements of other hotspot regions of the first hotspot group.Type: GrantFiled: December 14, 2020Date of Patent: June 14, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Fu An Tien, Hsu-Ting Huang, Ru-Gun Liu
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Patent number: 11353324Abstract: A method includes receiving, into a measurement tool, a substrate having a material feature, wherein the material feature is formed on the substrate according to a design feature. The method further includes applying a source signal on the material feature, collecting a response signal from the material feature by using the measurement tool, and with a computer connected to the measurement tool, calculating a simulated response signal from the design feature. The method further includes, with the computer, in response to determining that a difference between the collected response signal and the simulated response signal exceeds a predetermined value, causing the measurement tool to re-measure the material feature.Type: GrantFiled: December 19, 2019Date of Patent: June 7, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chui-Jung Chiu, Jen-Chieh Lo, Ying-Chou Cheng, Ru-Gun Liu
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Patent number: 11342193Abstract: In a method of forming a groove pattern extending in a first axis in an underlying layer over a semiconductor substrate, a first opening is formed in the underlying layer, and the first opening is extended in the first axis by directional etching to form the groove pattern.Type: GrantFiled: September 28, 2020Date of Patent: May 24, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ru-Gun Liu, Chih-Ming Lai, Wei-Liang Lin, Yung-Sung Yen, Ken-Hsien Hsieh, Chin-Hsiang Lin
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Publication number: 20220157605Abstract: A method of manufacturing a semiconductor device including operations of forming a first hard mask over an underlying layer on a substrate by a photolithographic and etching method, forming a sidewall spacer pattern having a first sidewall portion and a second sidewall portion on opposing sides of the first hard mask, etching the first sidewall portion, etching the first hard mask and leaving the second sidewall portion bridging a gap of the etched first hard mask, and processing the underlying layer using the second hard mask.Type: ApplicationFiled: January 31, 2022Publication date: May 19, 2022Inventors: Shih-Chun HUANG, Chiu-Hsiang CHEN, Ya-Wen YEH, Yu-Tien SHEN, Po-Chin CHANG, Chien-Wen LAI, Wei-Liang LIN, Ya Hui CHANG, Yung-Sung YEN, Li-Te LIN, Pinyen LIN, Ru-Gun LIU, Chin-Hsiang LIN
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Publication number: 20220155692Abstract: A method includes receiving a layout for fabricating a mask, determining a first target contour corresponding to a first set of process conditions, determining a second target contour corresponding to a second set of process conditions, simulating a first potential modification to the layout under the first set of process conditions to generate a first simulated contour, simulating a second potential modification to the layout under the second set of process conditions to generate a second simulated contour, evaluating costs of the first and second potential modifications based on comparing the first and second simulated contours to the first and second target contours, respectively, and providing the layout and one of the first and second potential modifications having a lower cost for fabricating the mask. The first set of process conditions is different from the second set of process conditions.Type: ApplicationFiled: February 7, 2022Publication date: May 19, 2022Inventors: Dong-Yo Jheng, Ken-Hsien Hsieh, Shih-Ming Chang, Chih-Jie Lee, Shuo-Yen Chou, Ru-Gun Liu
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Patent number: 11322362Abstract: A method for manufacturing a semiconductor device includes depositing a hard mask layer on an upper surface of an insulating layer. The hard mask layer is etched to form an opening in the hard mask layer. A via recess is formed in the insulating layer through the opening. A first photoresist layer is formed on the hard mask layer and in the via recess. The first photoresist layer is etched to form a photoresist plug in the via recess. Two opposite sides of the opening are etched to remove portions of the hard mask layer and thereby a portion of the upper surface of the insulating layer is exposed. The photoresist plug is removed. Metal is deposited in the via recess and on the exposed surface of the insulating layer. The metal is patterned.Type: GrantFiled: November 19, 2019Date of Patent: May 3, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Min Hsiao, Chih-Ming Lai, Chien-Wen Lai, Ya Hui Chang, Ru-Gun Liu
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Patent number: 11320747Abstract: Photolithography apparatus includes a radiation source, a mask to modify radiation from the radiation source so the radiation exposes photoresist layer disposed on a semiconductor substrate in patternwise manner, a wafer stage, and a controller. The wafer stage supports the semiconductor substrate. The controller determines target total exposure dose for the photoresist layer and target focus position for the photoresist layer; and controls exposure of first portion of the photoresist layer to first exposure dose of radiation at first focus position using first portion of the mask, moving the semiconductor substrate relative to the mask; and exposure of the first portion of the photoresist layer to second exposure dose of radiation using second portion of the mask at second focus position, and exposure of second portion of the photoresist layer to the second exposure dose at the second focus position using the first portion of the mask.Type: GrantFiled: December 14, 2020Date of Patent: May 3, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shinn-Sheng Yu, Ru-Gun Liu, Hsu-Ting Huang, Kenji Yamazoe, Minfeng Chen, Shuo-Yen Chou, Chin-Hsiang Lin
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Patent number: 11322393Abstract: A method includes depositing a second dielectric layer over a first dielectric layer, depositing a third dielectric layer over the second dielectric layer, patterning a plurality of first openings in the third dielectric layer, etching the second dielectric layer through the first openings to form second openings in the second dielectric layer, performing a plasma etching process directed at the second dielectric layer from a first direction, the plasma etching process extending the second openings in the first direction, and etching the first dielectric layer through the second openings to form third openings in the first dielectric layer.Type: GrantFiled: December 14, 2020Date of Patent: May 3, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Nien Su, Shu-Huei Suen, Jyu-Horng Shieh, Ru-Gun Liu
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Publication number: 20220108990Abstract: In an embodiment, a method (of manufacturing fins for a semiconductor device) includes: forming a first layer (on a semiconductor substrate) that has first spacers and etch stop layer (ESL) portions which are interspersed; forming second spacers on central regions of the first spacers and the ESL portions; removing exposed regions of the first spacers and the ESL portions and corresponding underlying portions of the semiconductor substrate; removing the second spacers resulting in corresponding first capped semiconductor fins and second capped semiconductor fins that are organized into first and second sets; each member of the first set having a first cap with a first etch sensitivity; and each member of the second set having a second cap with a different second etch sensitivity; and eliminating selected ones of the first capped semiconductor fins and selected ones of the second capped semiconductor fins.Type: ApplicationFiled: December 16, 2021Publication date: April 7, 2022Inventors: Chih-Liang CHEN, Chih-Ming LAI, Charles Chew-Yuen YOUNG, Chin-Yuan TSENG, Jiann-Tyng TZENG, Kam-Tou SIO, Ru-Gun LIU, Wei-Liang LIN, L. C. CHOU
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Patent number: 11294286Abstract: A photo mask for manufacturing a semiconductor device includes a first pattern extending in a first direction, a second pattern extending in the first direction and aligned with the first pattern, and a sub-resolution pattern extending in the first direction, disposed between an end of the first pattern and an end of the second pattern. A width of the first pattern and a width of the second pattern are equal to each other, and the first pattern and the second pattern are for separate circuit elements in the semiconductor device.Type: GrantFiled: February 27, 2019Date of Patent: April 5, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ru-Gun Liu, Chin-Hsiang Lin, Cheng-I Huang, Chih-Ming Lai, Chien-Wen Lai, Ken-Hsien Hsieh, Shih-Ming Chang, Yuan-Te Hou
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Patent number: 11289332Abstract: A method of fabricating a semiconductor device includes forming a hard mask layer over a substrate. A multi-layer resist is formed over the hard mask layer. The multi-layer resist is etched to form a plurality of openings in the multi-layer resist to expose a portion of the hard mask layer. Ion are directionally provided at an angle to the multi-layer resist to predominately contact sidewalls of the plurality of openings in the multi-layer resist rather than the hard mask layer. In one embodiment, the multi-layer resist is directionally etched by directing etch ions at an angle to predominately contact sidewalls of the plurality of openings in the multi-layer resist rather than the hard mask layer. In another embodiment, the multi-layer resist is directionally implanted by directing implant ions at an angle to predominately contact sidewalls of the plurality of openings in the multi-layer resist rather than the hard mask layer.Type: GrantFiled: July 15, 2019Date of Patent: March 29, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shih-Chun Huang, Chin-Hsiang Lin, Chien-Wen Lai, Ru-Gun Liu, Wei-Liang Lin, Ya Hui Chang, Yung-Sung Yen, Yu-Tien Shen, Ya-Wen Yeh
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Patent number: 11289376Abstract: The present disclosure provides a method for forming interconnect structures. The method includes providing a semiconductor structure including a substrate and a conductive feature formed in a top portion of the substrate; depositing a resist layer over the substrate, wherein the resist layer has an exposure threshold; providing a radiation with an incident exposure dose to the resist layer, wherein the incident exposure dose is configured to be less than the exposure threshold of the resist layer while a sum of the incident exposure dose and a reflected exposure dose from a top surface of the conductive feature is larger than the exposure threshold of the resist layer, thereby forming a latent pattern above the conductive feature; and developing the resist layer to form a patterned resist layer.Type: GrantFiled: June 4, 2020Date of Patent: March 29, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Ru-Gun Liu, Shih-Ming Chang, Hoi-Tou Ng
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Patent number: 11243472Abstract: A method includes receiving a layout that includes a shape to be formed on a photomask and determining a plurality of target lithographic contours for the shape, wherein the plurality of target lithographic contours includes a first target lithographic contour for a first set of process conditions and a second target lithographic contour for a second set of process conditions, performing a lithographic simulation of the layout to produce a first simulated contour at the first set of process conditions and a second simulated contour at the second set of process conditions, determining a first edge placement error between the first simulated contour and the first target lithographic contour and a second edge placement error between the second simulated contour and the second target lithographic contour, and determining a modification to the layout based on the first edge placement error and the second edge placement error.Type: GrantFiled: June 8, 2020Date of Patent: February 8, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Dong-Yo Jheng, Ken-Hsien Hsieh, Shih-Ming Chang, Chih-Jie Lee, Shuo-Yen Chou, Ru-Gun Liu
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Patent number: 11239078Abstract: A method of manufacturing a semiconductor device including operations of forming a first hard mask over an underlying layer on a substrate by a photolithographic and etching method, forming a sidewall spacer pattern having a first sidewall portion and a second sidewall portion on opposing sides of the first hard mask, etching the first sidewall portion, etching the first hard mask and leaving the second sidewall portion bridging a gap of the etched first hard mask, and processing the underlying layer using the second hard mask.Type: GrantFiled: July 6, 2020Date of Patent: February 1, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shih-Chun Huang, Chiu-Hsiang Chen, Ya-Wen Yeh, Yu-Tien Shen, Po-Chin Chang, Chien Wen Lai, Wei-Liang Lin, Ya Hui Chang, Yung-Sung Yen, Li-Te Lin, Pinyen Lin, Ru-Gun Liu, Chin-Hsiang Lin
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Patent number: 11222899Abstract: A semiconductor device including fins arranged so that: in a situation in which any given first one of the fins (first given fin) is immediately adjacent any given second one of the fins (second given fin), and subject to fabrication tolerance, there is a minimum gap, Gmin, between the first and second given fins; and the first and second given fins a minimum pitch, Pmin, that falls in a range as follows: (Gmin+(?90%)*T1)?Pmin?(Gmin+(?110%)*T1).Type: GrantFiled: July 1, 2020Date of Patent: January 11, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Liang Chen, Chih-Ming Lai, Charles Chew-Yuen Young, Chin-Yuan Tseng, Jiann-Tyng Tzeng, Kam-Tou Sio, Ru-Gun Liu, Wei-Liang Lin, L. C. Chou
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Patent number: 11204897Abstract: A computer-implemented method includes executing, using a computer, a process including a main thread that receives a layout file. The layout file includes a first plurality of tags and compressed information blocks. Each tag of the first plurality is associated with a compressed information block. The method further includes decompressing the compressed information blocks using sub-threads and thereby obtaining decompressed information blocks. The sub-threads are created by the main thread, and each sub-thread corresponds to a compressed information block. The decompressed information blocks are combined into decompressed layout information. The decompressed file is partitioned and each partition is provided to a node of a distributed computing system for performing layout correction.Type: GrantFiled: October 30, 2019Date of Patent: December 21, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Fu An Tien, Changsheng Ying, Hsu-Ting Huang, Ru-Gun Liu