Patents by Inventor Ruling ZHOU

Ruling ZHOU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device manufacturing method including implementing elements of memory unit and logic unit
    Patent number: 10014307
    Abstract: A method for manufacturing a semiconductor device includes providing a substrate, a first conductor, a second conductor, a first dielectric, a second dielectric, and a designated region. The first conductor is positioned between the first dielectric and the substrate. The second conductor is positioned between the second dielectric and the substrate. The first designated region is positioned in the substrate. The method includes providing a conductive material layer, which completely covers the first dielectric and the second dielectric. The method includes partially removing the conductive material layer to form a third conductor and a fourth conductor. The first dielectric is positioned between the third conductor and the first conductor. The fourth conductor directly contacts the designated region. The method includes implementing a memory unit using the first conductor and the third conductor and includes implementing a logic unit using the second conductor and the designated region.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: July 3, 2018
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: YiPeng Chan, Jieqiong Dong, Huajun Jin, Ruling Zhou, Shibi Guo, Bongkil Kim
  • SEMICONDUCTOR DEVICE, RELATED MANUFACTURING METHOD, AND RELATED ELECTRONIC DEVICE
    Publication number: 20160190148
    Abstract: A method for manufacturing a semiconductor device includes providing a substrate, a first conductor, a second conductor, a first dielectric, a second dielectric, and a designated region. The first conductor is positioned between the first dielectric and the substrate. The second conductor is positioned between the second dielectric and the substrate. The first designated region is positioned in the substrate. The method includes providing a conductive material layer, which completely covers the first dielectric and the second dielectric. The method includes partially removing the conductive material layer to form a third conductor and a fourth conductor. The first dielectric is positioned between the third conductor and the first conductor. The fourth conductor directly contacts the designated region. The method includes implementing a memory unit using the first conductor and the third conductor and includes implementing a logic unit using the second conductor and the designated region.
    Type: Application
    Filed: December 7, 2015
    Publication date: June 30, 2016
    Inventors: YiPeng CHAN, Jieqiong DONG, Huajun JIN, Ruling ZHOU, Shibi GUO, Bongkil KIM