Patents by Inventor Ru Yin Ng

Ru Yin Ng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220011960
    Abstract: Per channel thermal management techniques are described herein. In one example, a memory controller receives channel temperature information for one or more channels of one or more dies in the stack. The memory controller can then throttle commands at a channel-level based on the channel temperature information. In one example, row commands and column commands to a channel are throttled at independent rates based on the channel temperature information. In one example, a row command throttling rate or column command throttling rate is based on a ratio of alternating on-time to off time of throttling signals, or a window of time in which commands are enabled or disabled to a channel. In one example, the row and column command throttling signals can be staggered across channels or pseudo channels.
    Type: Application
    Filed: September 25, 2021
    Publication date: January 13, 2022
    Inventors: Chang Kian TAN, Ru Yin NG, Saravanan SETHURAMAN, Kuljit S. BAINS
  • Patent number: 10146249
    Abstract: A control system controls First-In First-Out (FIFO) settings of a receiving system. The control system includes a FIFO settings controller that receives a first signal indicative of a first frequency of data received by the receiving system. The FIFO settings controller receives a second signal indicative of a second frequency of a clock that reads the data received by the receiving system. The FIFO settings controller determines a difference (e.g., a parts-per-million (PPM) difference) between the first frequency and the second frequency. The FIFO settings controller sends a third signal indicative of instructions to adjust FIFO configuration settings based on the PPM difference.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: December 4, 2018
    Assignee: Altera Corporation
    Inventors: Han Hua Leong, Ru Yin Ng, Geok Sun Chong, David W. Mendel
  • Publication number: 20180088622
    Abstract: A control system controls First-In First-Out (FIFO) settings of a receiving system. The control system includes a FIFO settings controller that receives a first signal indicative of a first frequency of data received by the receiving system. The FIFO settings controller receives a second signal indicative of a second frequency of a clock that reads the data received by the receiving system. The FIFO settings controller determines a difference (e.g., a parts-per-million (PPM) difference) between the first frequency and the second frequency. The FIFO settings controller sends a third signal indicative of instructions to adjust FIFO configuration settings based on the PPM difference.
    Type: Application
    Filed: September 23, 2016
    Publication date: March 29, 2018
    Inventors: Han Hua Leong, Ru Yin Ng, Geok Sun Chong, David W. Mendel
  • Patent number: 9891653
    Abstract: An integrated circuit die includes interface and adapter circuits. The interface circuit exchanges data with an external device outside the integrated circuit die using a first clock signal. The interface circuit has a clock signal generation circuit to generate the first clock signal based on a second clock signal. The adapter circuit exchanges the data with the interface circuit. A frequency of the second clock signal is changed in response to an indication of a change in a data rate of the data. The adapter circuit causes the interface circuit to provide an adjustment to the first clock signal after the frequency of the second clock signal changes. The adapter circuit prevents the exchange of the data between the interface circuit and the external device until the adapter circuit receives an indication of completion of the adjustment to the first clock signal.
    Type: Grant
    Filed: June 15, 2015
    Date of Patent: February 13, 2018
    Assignee: Altera Corporation
    Inventors: Ru Yin Ng, Gary Wallichs, Keith Duwel
  • Publication number: 20160363954
    Abstract: An integrated circuit die includes interface and adapter circuits. The interface circuit exchanges data with an external device outside the integrated circuit die using a first clock signal. The interface circuit has a clock signal generation circuit to generate the first clock signal based on a second clock signal. The adapter circuit exchanges the data with the interface circuit. A frequency of the second clock signal is changed in response to an indication of a change in a data rate of the data. The adapter circuit causes the interface circuit to provide an adjustment to the first clock signal after the frequency of the second clock signal changes. The adapter circuit prevents the exchange of the data between the interface circuit and the external device until the adapter circuit receives an indication of completion of the adjustment to the first clock signal.
    Type: Application
    Filed: June 15, 2015
    Publication date: December 15, 2016
    Applicant: ALTERA CORPORATION
    Inventors: Ru Yin Ng, Gary Wallichs, Keith Duwel