Patents by Inventor Ruben Attia

Ruben Attia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System for implementing shared lock free memory implementing composite assignment
    Patent number: 11646063
    Abstract: It is an object of the disclosed technique to provide a novel method and system for shared concurrent access to a memory cell. In accordance with the disclosed technique, there is thus provided a system for shared concurrent access to a memory cell, which includes at least one shared memory cell, an evaluator and a plurality of processing agents coupled to the input of the evaluator. The evaluator is further coupled with the at least one memory cell. The evaluator is configured to evaluate an expression for performing multiple concurrent composite assignments on the at least one shared memory cell. The evaluator further allows each of the plurality of processing agents to perform concurrent composite assignments on the at least one shared memory cell. The composite assignments do not include a read operation of the at least one shared memory cell by the plurality of processing agents.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: May 9, 2023
    Assignee: JERUSALEM COLLEGE OF TECHNOLOGY
    Inventors: Shimon Mizrahi, Raphael Berakhael Yehezkael, Ruben Attia, Erez Lax, Devora Berlowitz, Moshe Goldstein, David Dayan
  • SYSTEM FOR IMPLEMENTING SHARED LOCK FREE MEMORY IMPLEMENTING COMPOSITE ASSIGNMENT
    Publication number: 20210225416
    Abstract: It is an object of the disclosed technique to provide a novel method and system for shared concurrent access to a memory cell. In accordance with the disclosed technique, there is thus provided a system for shared concurrent access to a memory cell, which includes at least one shared memory cell, an evaluator and a plurality of processing agents coupled to the input of the evaluator. The evaluator is further coupled with the at least one memory cell. The evaluator is configured to evaluate an expression for performing multiple concurrent composite assignments on the at least one shared memory cell. The evaluator further allows each of the plurality of processing agents to perform concurrent composite assignments on the at least one shared memory cell. The composite assignments do not include a read operation of the at least one shared memory cell by the plurality of processing agents.
    Type: Application
    Filed: July 24, 2019
    Publication date: July 22, 2021
    Applicant: JERUSALEM COLLEGE OF TECHNOLOGY
    Inventors: Shimon MIZRAHI, Raphael Berakhael YEHEZKAEL, Ruben ATTIA, Erez LAX, Devora BERLOWITZ, Moshe GOLDSTEIN, David DAYAN
  • Timing based camouflage circuit
    Patent number: 10396043
    Abstract: In one embodiment, a chip comprising a circuit, the circuit comprising a plurality of components, wherein the circuit is adapted to perform a function that is dependent on timing behavior of the circuit, and wherein a geometry of a layout of the circuit is substantially the same as another geometry of another layout of another circuit adapted to perform another function that is dependent on different timing behavior.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: August 27, 2019
    Assignee: Cisco Technology, Inc.
    Inventors: David Darmon, Avi Klein, Yehuda Salmon, Aharon Grabovsky, Ruben Attia
  • TIMING BASED CAMOUFLAGE CIRCUIT
    Publication number: 20190189571
    Abstract: In one embodiment, a chip comprising a circuit, the circuit comprising a plurality of components, wherein the circuit is adapted to perform a function that is dependent on timing behavior of the circuit, and wherein a geometry of a layout of the circuit is substantially the same as another geometry of another layout of another circuit adapted to perform another function that is dependent on different timing behavior.
    Type: Application
    Filed: February 26, 2019
    Publication date: June 20, 2019
    Inventors: David Darmon, Avi Klein, Yehuda Salmon, Aharon Grabovsky, Ruben Attia
  • Timing based camouflage circuit
    Patent number: 10262956
    Abstract: In one embodiment, a chip comprising a circuit, the circuit comprising a plurality of components, wherein the circuit is adapted to perform a function that is dependent on timing behavior of the circuit, and wherein a geometry of a layout of the circuit is substantially the same as another geometry of another layout of another circuit adapted to perform another function that is dependent on different timing behavior.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: April 16, 2019
    Assignee: Cisco Technology, Inc.
    Inventors: David Darmon, Avi Klein, Yehuda Salmon, Aharon Grabovsky, Ruben Attia
  • TIMING BASED CAMOUFLAGE CIRCUIT
    Publication number: 20180247902
    Abstract: In one embodiment, a chip comprising a circuit, the circuit comprising a plurality of components, wherein the circuit is adapted to perform a function that is dependent on timing behavior of the circuit, and wherein a geometry of a layout of the circuit is substantially the same as another geometry of another layout of another circuit adapted to perform another function that is dependent on different timing behavior.
    Type: Application
    Filed: July 3, 2017
    Publication date: August 30, 2018
    Inventors: David DARMON, Avi Klein, Yehuda Salmon, Aharon Grabovsky, Ruben Attia