Abstract: Disclosed are a method, system, and/or apparatus to perform clock jitter and power supply noise analysis. In one embodiment, a method may include receiving a first signal, which may be a clock signal, then generating a second signal based on the first signal. The method may further include delaying the second signal by a base delay and/or a series of fine delays. The method may also include taking measurements of the delayed second signal and comparing those measurements to theoretical measurements of the second signal that would occur if the first signal were noise-free. The method may further include determining, based on the measurements and the comparison thereof, whether noise is present, whether the noise is high frequency or low frequency noise, and whether the noise is due to clock jitter and/or power supply deviations.

Abstract: A system and method are provided for measuring an integrated circuit age. A first clock generator is provided for generating a first clock signal and a second clock generator is provided for generating a second clock signal. Further, a phase detector in communication with the first clock generator and the second clock generator is provided for receiving the first clock signal from the first clock generator and the second clock signal from the second clock generator, and outputting a phase difference signal that is capable of being used as a measure of an integrated circuit age. Still yet, a circuit in communication with the phase detector and the first clock generator is provided for receiving the first clock signal from the first clock generator and the phase difference signal from the phase detector and for synchronizing the phase difference signal from the phase detector with the first clock signal from the first clock generator.

Abstract: Disclosed are a method, system, and/or apparatus to perform clock jitter and power supply noise analysis. In one embodiment, a method may include receiving a first signal, which may be a clock signal, then generating a second signal based on the first signal. The method may further include delaying the second signal by a base delay and/or a series of fine delays. The method may also include taking measurements of the delayed second signal and comparing those measurements to theoretical measurements of the second signal that would occur if the first signal were noise-free. The method may further include determining, based on the measurements and the comparison thereof, whether noise is present, whether the noise is high frequency or low frequency noise, and whether the noise is due to clock jitter and/or power supply deviations.

Abstract: A system and method are provided for measuring an integrated circuit age. A first clock generator is provided for generating a first dock signal. Additionally, a second clock generator is provided for generating a second clock signal. Further, a phase detector is provided that is in communication with the first dock generator and the second dock generator. The phase detector is operable for receiving the first clock signal from the first clock generator and the second clock signal from the second dock generator, and outputting a phase difference signal. Still yet, a circuit is provided that is in communication with the phase detector and the first clock generator. The circuit is operable for receiving the first clock signal from the first clock generator and the phase difference signal from the phase detector. The circuit is further operable for synchronizing the phase difference signal from the phase detector with the first dock signal from the first clock generator.

Abstract: A circuit includes an input stage, an output stage, and a delay stage. The input stage is operative to receive a clock signal and a first and second input signal. The output stage is operative to receive the clock signal. The output stage is also operative to generate a first and second output signal based on the clock signal and the first and second input signals. The delay stage is operatively coupled to the input and output stages. The delay stage includes a first and second branch. The second branch includes at least one more delay element than the first branch.

Abstract: A scan flip-flop circuit including a data input, a scan input, a data output, a flip-flop, a multiplexer and a delay element is provided. The multiplexer allows selection of either the scan input or the data input for presentation at the input of the flip-flop. The flip-flop provides an output signal at the output of the scan flip-flop. The delay element is in a signal path between the scan input and the input of the flip-flop, and provides a signal propagation delay between the scan input and the input of the flip-flop. The delay between the scan input and the input of the flip-flop is substantially larger than the signal propagation delay between the data input and the input of the flip-flop. The delay in the scan path reduces the need for external buffers to avoid hold-time violations during scan testing of integrated circuits.

Abstract: A scan flip-flop circuit including a data input, a scan input, a data output, a flip-flop, a multiplexer and a delay element is provided. The multiplexer allows selection of either the scan input or the data input for presentation at the input of the flip-flop. The flip-flop provides an output signal at the output of the scan flip-flop. The delay element is in a signal path between the scan input and the input of the flip-flop, and provides a signal propagation delay between the scan input and the input of the flip-flop. The delay between the scan input and the input of the flip-flop is substantially larger than the signal propagation delay between the data input and the input of the flip-flop. The delay in the scan path reduces the need for external buffers to avoid hold-time violations during scan testing of integrated circuits.

Abstract: A circuit includes an input stage, an output stage, and a delay stage. The input stage is operative to receive a clock signal and a first and second input signal. The output stage is operative to receive the clock signal. The output stage is also operative to generate a first and second output signal based on the clock signal and the first and second input signals. The delay stage is operatively coupled to the input and output stages. The delay stage includes a first and second branch. The second branch includes at least one more delay element than the first branch.