Abstract: In one embodiment, a cache comprises a data memory comprising a plurality of data entries, each data entry having capacity to store a cache block of data, and a cache control unit coupled to the data memory. The cache control unit is configured to dynamically allocate a given data entry in the data memory to store a cache block being cached or to store data that is not being cache but is being staged for retransmission on an interface to which the cache is coupled.

Abstract: In one embodiment, a system comprises at least one processor and a peripheral interface controller coupled to the processor. Further coupled to receive transactions from a peripheral interface, the peripheral interface controller is configured to accumulate freed credits for a given transaction type of a plurality of transaction types that are not yet returned to a transmitter on the peripheral interface. The peripheral interface controller is also configured to cause transmission of a flow control update transaction on the peripheral interface responsive to a number of the freed credits exceeding a threshold amount that is less than a total number of credits allocated to the given transaction type.

Abstract: These and other aspects of the present invention will be better described with reference to the Detailed Description and the accompanying figures. A method and apparatus for out-of-order processing of packets using linked lists is described. In one embodiment, the method includes receiving packets in a global order, the packets being designated for different ones of a plurality of reorder contexts. The method also includes storing information regarding each of the packets in a shared reorder buffer. The method also includes for each of the plurality of reorder contexts, maintaining a reorder context linked list that records the order in which those of the packets that were designated for that reorder context and that are currently stored in the shared reorder buffer were received relative to the global order.

Abstract: In various embodiments, an apparatus comprises a plurality of agents and an interconnect. In one embodiment, the plurality of agents includes first through fourth agents. The interconnect comprises a plurality of segments that are switchable (e.g. using a plurality of selection circuits) to form communication paths between the agents, and a first segment is included in a first communication path from the first agent to the second agent, and is also included in a second communication path from the third agent to the fourth agent. In another embodiment, each segment is driven by a selection circuit. At least one selection circuit has at least one segment and an output from at least one agent as inputs. In yet another embodiment, an arbiter is configured to determine a communication path on the interconnect for each requesting agent to the destination agent over the segments.

Abstract: In various embodiments, an apparatus comprises a plurality of agents and an interconnect. In one embodiment, the plurality of agents includes first through fourth agents. The interconnect comprises a plurality of segments that are switchable (e.g. using a plurality of selection circuits) to form communication paths between the agents, and a first segment is included in a first communication path from the first agent to the second agent, and is also included in a second communication path from the third agent to the fourth agent. In another embodiment, each segment is driven by a selection circuit. At least one selection circuit has at least one segment and an output from at least one agent as inputs. In yet another embodiment, an arbiter is configured to determine a communication path on the interconnect for each requesting agent to the destination agent over the segments.

Abstract: In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations.

Abstract: In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations.

Abstract: In one embodiment, a switch is configured to be coupled to an interconnect. The switch comprises a plurality of storage locations and an arbiter control circuit coupled to the plurality of storage locations. The plurality of storage locations are configured to store a plurality of requests transmitted by a plurality of agents. The arbiter control circuit is configured to arbitrate among the plurality of requests stored in the plurality of storage locations. A selected request is the winner of the arbitration, and the switch is configured to transmit the selected request from one of the plurality of storage locations onto the interconnect. In another embodiment, a system comprises a plurality of agents, an interconnect, and the switch coupled to the plurality of agents and the interconnect. In another embodiment, a method is contemplated.

Abstract: In various embodiments, an apparatus comprises a plurality of agents and an interconnect. In one embodiment, the plurality of agents includes first through fourth agents. The interconnect comprises a plurality of segments that are switchable (e.g. using a plurality of selection circuits) to form communication paths between the agents, and a first segment is included in a first communication path from the first agent to the second agent, and is also included in a second communication path from the third agent to the fourth agent. In another embodiment, each segment is driven by a selection circuit. At least one selection circuit has at least one segment and an output from at least one agent as inputs. In yet another embodiment, an arbiter is configured to determine a communication path on the interconnect for each requesting agent to the destination agent over the segments.

Abstract: A method and apparatus for transmitting unscheduled flow control, in packet form, between two chips are described. In one embodiment, a method includes reading a status of a buffer used to receive network packets transmitted from a different chip. The method further includes transmitting to said different chip an unscheduled flow control packet including information about the status of the buffer. In an embodiment, a chip includes a packet buffer to store network packets transmitted from a different chip, wherein the packet buffer is associated with one or more of a plurality of ports through which the network packets travel. The chip also includes control circuitry, coupled with a packet data bus to receive said network packets from the different chip, and coupled with an unscheduled flow control packet bus to generate and transmit unscheduled flow control packets to the different chip, wherein the unscheduled flow control packets contain information relating to the packet buffer.

Abstract: A method and apparatus for transmitting unscheduled flow control, in packet form, between two chips are described. In one embodiment, a method includes reading a status of a buffer used to receive network packets transmitted from a different chip. The method further includes transmitting to said different chip an unscheduled flow control packet including information about the status of the buffer.

Abstract: In a fibre channel network environment wherein an arbitrated loop is provided a switchable connection with another arbitrated loop, a technique and corresponding apparatus are provided for controlling signal paths through the hubs stack between any two devices such that routing of a signal and interactive communication can be carried out transparently to the fibre channel network without excessive overhead, and wherein control is changed in an orderly manner such that end-to-end device connections are unaware that they are not connected to the same hub. A switched arbitrated loop (SAL) according to the invention provides the concurrent bandwidth resource of a fabric switch without the extra features which would increase design cost and operational overhead. In a specific embodiment, a switched arbitrated loop supports only 126 nodes for stations (plus one fabric port) in a single loop topology.

Abstract: A distributed arbitration scheme for a network. Ports in a network device determine which port in a set of ports may broadcast a packet onto a bus in the network device. A method of transmitting data between a set of ports sharing a bus in hub is described. The set of ports includes a first port, and the method comprises the first port receiving a packet, the first port requesting the bus, and, if another port is requesting the bus, the first port transmitting the packet to the bus if the first port has not transmitted a packet later than the another port requesting the bus. A system using two clocks of different speeds in a network device. The hub has at least a port. The port has an internal data path having a first width. A bus is coupled to the port. The bus has a data path that has a second width. The second width is greater than the first width. The hub includes a first clock that has a first frequency and is coupled to circuitry in the port for clocking internal data transfers.

Abstract: A method for tuning an adaptive equalizer in order to receive digital signals from a transmission medium both coarse and fine tuning methods to adaptively equalize a signal received from the transmission medium. The coarse tuning method adjusts an equalizer such that the post equalized signal starts to resemble a known data pattern, such as an MLT3 data pattern. The coarse tuning method monitors and corrects for several things: illegal transitions, over equalization, statistical data pattern anomalies and saturation conditions. Fine tuning methods operate concurrently with the coarse tuning methods and function from the point at which the coarse tuning methods stop being efficient. Additionally, the fine tuning methods hold the waveform locked in. In addition to coarse tuning and fine tuning of the equalizer, the present invention also adjusts gain of the overall signal such that the post equalized signal is always a certain amplitude.

Abstract: A method for tuning an adaptive equalizer in order to receive digital signals from a transmission medium both coarse and fine tuning methods to adaptively equalize a signal received from the transmission medium. The coarse tuning method adjusts an equalizer such that the post equalized signal starts to resemble a known data pattern, such as an MLT3 data pattern. The coarse tuning method monitors and corrects for several things: illegal transitions, over equalization, statistical data pattern anomalies and saturation conditions. Fine tuning methods operate concurrently with the coarse tuning methods and function from the point at which the coarse tuning methods stop being efficient. Additionally, the fine tuning methods hold the waveform locked in. In addition to coarse tuning and fine tuning of the equalizer, one embodiment also adjusts gain of the overall signal such that the post equalized signal is always a certain amplitude.

Abstract: A method for tuning an adaptive equalizer in order to receive digital signals from a transmission medium both coarse and fine tuning methods to adaptively equalize a signal received from the transmission medium. The coarse tuning method adjusts an equalizer such that the post equalized signal starts to resemble a known data pattern, such as an MLT3 data pattern. The coarse tuning method monitors and corrects for several things: illegal transitions, over equalization, statistical data pattern anomalies and saturation conditions. Fine tuning methods operate concurrently with the coarse tuning methods and function from the point at which the coarse tuning methods stop being efficient. Additionally, the fine tuning methods hold the waveform locked in. In addition to coarse tuning and fine tuning of the equalizer, the present invention also adjusts gain of the overall signal such that the post equalized signal is always a certain amplitude.

Abstract: A current-controlled oscillator with first and second differential comparators (640, 840) serving as inputs, first and second voltage independent multi-layered integrated capacitors (600, 800) corresponding to the first and second comparators (640, 840), and a RS latch (700) for switching operation between the two comparators (640, 840) thereby achieving oscillation. The multi-layered integrated capacitors (600, 800) are designed to provide voltage independent capacitance.

Abstract: A method and apparatus is provided allowing a dual-speed network adapter to connect to the same physical connector without the use of mechanical or electro-mechanical switches. On the transmit path, the invention uses a differential amplifier buffer (130) to selectively couple a high speed transmit paths to the network, with the differential amplifier connected to the same output impedance as one of the two driver circuits. On the receive path, the invention allows data to be received in parallel by two receiver circuits, with one circuit isolated from the other with a pair of very high input impedance emitter/followers (40, 50).