Abstract: Federated learning accelerators and related methods are disclosed. An example edge device includes neural network trainer circuitry to train a neural network to generate a model update for a machine learning model using local data; a federated learning accelerator to perform one or more federated learning workloads associated with the training; and model update provider circuitry to transmit the model update to an aggregator device.

Abstract: Various aspects of techniques, systems, and use cases include provide instructions for operating an autonomous mobile robot (AMR). A technique may include capturing audio or video data using a sensor of the AMR, performing a classification of the audio or video data using a trained classifier, and identifying a coordinate of an environmental map corresponding to a location of the audio or video data. The technique may include updating the environmental map to include the classification as metadata corresponding to the coordinate. The technique may include communicating the updated environmental map to an edge device.

Abstract: Various systems and methods for detecting risk conditions in a physical workspace. An apparatus can include an interface to receive smart sensor signals from at least one autonomous mobile entity (AME) in the physical workspace. The apparatus can also include processing circuitry coupled to the interface to detect a risk condition associated with the at least one AME, based on the smart sensor signals, relative to a user device associated with a human present in the physical workspace. The processing circuitry can also detect a direction of the risk condition relative to the user device and cause a notification to the first user device. The notification can indicate the direction of the risk condition relative to the user device. Other systems, methods and apparatuses are described.

Abstract: In an embodiment, a processor includes a plurality of cores to independently execute instructions, at least one graphics engine to independently execute graphics instructions, and a power controller including a duty cycle logic to set a duty cycle having a cycle time formed of an active time window in which at least some of the plurality of cores are to be active and an idle time window in which the plurality of cores are to be in a low power state. The duty cycle logic may adjust a duration of at least one of an active time window and an inactive time window based on interrupt information to accommodate an impending interrupt within the active time window. Other embodiments are described and claimed.

Abstract: In an embodiment, a processor includes a plurality of cores to independently execute instructions, at least one graphics engine to independently execute graphics instructions, and a power controller including an alignment logic to cause at least one workload to be executed on a first core to be rescheduled to a different time to enable the plurality of cores to be active during an active time window and to be in a low power state during an idle time window. Other embodiments are described and claimed.

Abstract: In an embodiment, a processor includes a plurality of cores to independently execute instructions, at least one graphics engine to independently execute graphics instructions, and a power controller including a duty cycle logic to set a duty cycle having a cycle time formed of an active time window in which at least some of the plurality of cores are to be active and an idle time window in which the plurality of cores are to be in a low power state. The duty cycle logic may adjust a duration of at least one of an active time window and an inactive time window based on interrupt information to accommodate an impending interrupt within the active time window. Other embodiments are described and claimed.

Abstract: In an embodiment, a processor includes a plurality of cores to independently execute instructions, at least one graphics engine to independently execute graphics instructions, and a power controller including an alignment logic to cause at least one workload to be executed on a first core to be rescheduled to a different time to enable the plurality of cores to be active during an active time window and to be in a low power state during an idle time window. Other embodiments are described and claimed.

Abstract: In some embodiments, a control interface and associated control entity are provided to synchronize CPU activities to CPU power delivery network such as VR mode of operation, based on CPU power demands or the prediction of actual CPU current consumption. In some embodiments, the synchronization is controlled in such timely fashion so that the power states or power-related events are entered by a CPU (or core) based on characteristics of a VR supplying power to the CPU (or core).