Patents by Inventor Ruchir Puri
Ruchir Puri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8271920Abstract: Exemplary embodiments include a computer implemented method for large block and structured synthesis, the method including determining initial design data from starting points for a synthesis flow, receiving user-directed structuring is incorporated into the synthesis flow, applying logical synthesis on the initial design data, applying a physical design on the initial design data, determining whether circuit design parameters have been met and in response to circuit design parameters not being met, adjusting the circuit design parameters.Type: GrantFiled: August 25, 2010Date of Patent: September 18, 2012Assignee: International Business Machines CorporationInventors: Minsik Cho, Victor N. Kravets, Smita Krishnaswamy, Dorothy Kucar, Jagannathan Narasimhan, Ruchir Puri, Haifeng Qian, Haoxing Ren, Chin Ngai Sze, Louise H. Trevillyan, Hua Xiang, Matthew M. Ziegler
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Patent number: 8261226Abstract: A scaled network flow graph is constructed, including a plurality of nodes and a plurality of edges. The plurality of nodes correspond to: (i) a pseudo device pin node for each pair of corresponding paired device pins; (ii) a pseudo bottom surface metal node for each pair of bottom surface metal pins on each of multiple routing layers; (iii) a source node connected to each of the pseudo device pin nodes; (iv) a sub-sink node for each pair of the paired bottom surface metal pins (each of the sub-sink nodes is connected to corresponding ones of the pseudo bottom surface metal nodes for each of the pairs of bottom surface metal pins on each of the multiple routing layers); and (v) a sink node connected to the sub-sink nodes. A capacity and a cost are assigned to each of the edges of the scaled network flow graph. A min-cost-max-flow technique is applied to the scaled network flow graph with the assigned capacities and costs to obtain an optimal flow solution.Type: GrantFiled: July 20, 2011Date of Patent: September 4, 2012Assignee: International Business Machines CorporationInventors: Wiren Dale Becker, Ruchir Puri, Haoxing Ren, Hua Xiang, Tingdong Zhou
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Publication number: 20120054698Abstract: A computer-executed method is disclosed which recognizes two circuits, an original and a modified circuit, with the original circuit having a first logic and the modified circuit having a second logic. The second logic is obtained by converting a modified specification into a preliminary gate-level form. The second logic contains at least one desired logic change relative to the first logic in order to realize the modified specification. The method includes detecting an equivalence line in the original circuit, such that the first and second logic are equivalent from the circuit inputs to the equivalence line, and finding at least one point of change amongst the logic gates that are neighboring the equivalence line.Type: ApplicationFiled: August 25, 2010Publication date: March 1, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Eli Arbel, David Geiger, Victor Kravets, Smita Krishnaswamy, Ruchir Puri, Haoxing Ren
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Publication number: 20120054699Abstract: Exemplary embodiments include a computer implemented method for large block and structured synthesis, the method including determining initial design data from starting points for a synthesis flow, receiving user-directed structuring is incorporated into the synthesis flow, applying logical synthesis on the initial design data, applying a physical design on the initial design data, determining whether circuit design parameters have been met and in response to circuit design parameters not being met, adjusting the circuit design parameters.Type: ApplicationFiled: August 25, 2010Publication date: March 1, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Minsik Cho, Victor N. Kravets, Smita Krishnaswamy, Dorothy Kucar, Jagannathan Narasimhan, Ruchir Puri, Haifeng Qian, Haoxing Ren, Chin Ngai Sze, Louise H. Trevillyan, Hua Xiang, Matthew M. Ziegler
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Patent number: 8122400Abstract: A computer executed method is disclosed which accepts an original circuit with an original logic, accepts a modified circuit, and synthesizes a difference circuit. The difference circuit represents changes that implement the modified circuit's logic for the original circuit. The synthesis may locate an output-side boundary in the original logic in such a manner that the original logic is free of logic changes in between the output-side boundary and the primary output elements of the original circuit. The disclosed synthesis may also locate an input-side boundary in the original logic in such a manner that the original logic is free of logic changes in between the input-side boundary and the primary input elements of the original circuit. A computer program products are also disclosed. The computer program product contains a computer useable medium having a computer readable program code embodied therein.Type: GrantFiled: July 2, 2009Date of Patent: February 21, 2012Assignee: International Business Machines CorporationInventors: Jeremy T. Hopkins, John M. Isakson, Joachim Keinert, Smita Krishnaswamy, Nilesh A. Modi, Ruchir Puri, Haoxing Ren, David L. Rude
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Patent number: 8117568Abstract: Methods, apparatus and computer program products provide a fast and accurate model for simulating the effects of chemical mechanical polishing (CMP) steps during fabrication of an integrated circuit by generating a design of an integrated circuit; while generating the design of the integrated circuit, using a simplified model to predict at least one physical characteristic of the integrated circuit which results from a CMP processing step to be used during manufacture of the integrated circuit, wherein the simplified model is derived from simulations performed prior to the design generation activities using a comprehensive simulation program used to model the physical characteristic; predicting performance of the integrated circuit using the predicted physical characteristic; and adjusting the design of the integrated circuit in dependence on the performance prediction.Type: GrantFiled: September 25, 2008Date of Patent: February 14, 2012Assignee: International Business Machines CorporationInventors: Hua Xiang, Laertis Economikos, Mohammed F. Fayaz, Stephen E. Greco, Patricia A. O'Neil, Ruchir Puri
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Patent number: 8104014Abstract: Power, routability and electromigration have become crucial issues in modem microprocessor designs. In high performance designs, clocks are the highest consumer of power. Arranging clocking components with regularity so as to minimize the capacitance of the clock nets can help reduce clock power, however, it may hurt performance due to some loss of flexibility in physically placing those components. The present invention provides techniques to optimally design a clock network by logically assigning clusters of the latches to respective clock distribution structures, placing clock pins at favored pin locations, and placing clock distribution structures directly underneath the clock pins. The clock distribution structures may be moved to favored distribution locations along the clock stripes, and new optimal clustering generated between the latches and the clock distribution structures. These three optimizations are preferably repeated iteratively to derive a local optimal solution for the clock network.Type: GrantFiled: January 30, 2008Date of Patent: January 24, 2012Assignee: International Business Machines CorporationInventors: Ruchir Puri, Haifeng Qian, Chin Ngai Sze, James Warnock
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Publication number: 20120017186Abstract: Exemplary embodiments include a method for modifying a circuit synthesis flow having automated instructions, the method including receiving circuit design input for a circuit design, receiving custom specifications to the circuit design input, synthesizing high level logic from the circuit design input, placing logic on the circuit design, refining the circuit design and generating a circuit description from the circuit design.Type: ApplicationFiled: July 14, 2010Publication date: January 19, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael D. Amundson, Dorothy Kucar, Ruchir Puri, Chin Ngai Sze, Matthew M. Ziegler
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Patent number: 8053819Abstract: An IC structure having reduced power loss and/or noise includes two or more active semiconductor regions stacked in a substantially vertical dimension, each active semiconductor region including an active layer. The IC structure further includes two or more voltage supply planes, each of the voltage supply planes corresponding to a respective one of the active layers.Type: GrantFiled: May 15, 2008Date of Patent: November 8, 2011Assignee: International Business Machines CorporationInventors: Kerry Bernstein, Paul W. Coteus, Philip George Emma, Allan Mark Hartstein, Stephen V. Kosonocky, Ruchir Puri, Mark B. Ritter
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Patent number: 8020134Abstract: In one embodiment, the invention is a method and apparatus for parallel processing of semiconductor chip designs. One embodiment of a method for processing a semiconductor chip design includes flattening a netlist corresponding to the semiconductor chip design, performing logic clustering on one or more logic elements incorporated in the flattened netlist to generate one or more clusters, partitioning the semiconductor chip design in accordance with the one or more clusters, and designing the individual partitions in parallel.Type: GrantFiled: February 22, 2008Date of Patent: September 13, 2011Assignee: International Business Machines CorporationInventors: Michael W. Dotson, Anthony DeGroff Drumm, Dazhuang J. Ma, Ruchir Puri, Louise H. Trevillyan
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Patent number: 8010926Abstract: Power, routability and electromigration have become crucial issues in modern microprocessor designs. In high performance designs, clocks are the highest consumer of power. Arranging clocking components with regularity so as to minimize the capacitance on the clock nets can help reduce clock power, however, it may hurt performance due to some loss of flexibility in physically placing those components. The present invention provides techniques to optimally place clock components in a regular fashion so as to minimize clock power within a performance constraint. A rectangular grid is created and clock distribution structures are assigned to the grid intersection points. Latches are then located around the clock distribution structures to minimize an overall distance for connections between the latches and respective clock distribution structures. The horizontal and vertical pitches of the grid may be independently adjusted to achieve a more uniform spread of the clock distribution structures.Type: GrantFiled: January 30, 2008Date of Patent: August 30, 2011Assignee: International Business Machines CorporationInventors: Charles J. Alpert, Ruchir Puri, Shyam Ramji, Ashish K. Singh, Chin Ngai Sze
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Patent number: 7930669Abstract: The present invention provides a method, system and program product for mitigating effects of interconnect variability during a design stage of a chip. Under the technique of the present invention, a global and detailed routing of interconnects of the chip are determined. Thereafter, a dummy fill estimation and a grid based metal density estimation are performed. Then, based on a CMP model, a variable map of metal thicknesses is obtained. Based on the variable map, wiring nets of the chip that are sensitive to metal variability (e.g., that fail to meet timing closure due to metal thickness loss/gain in the CMP process) are identified. These wiring nets are then re-routed for optimization of the chip.Type: GrantFiled: September 24, 2008Date of Patent: April 19, 2011Assignee: International Business Machines CorporationInventors: Mark A. Lavin, Ruchir Puri, Louise H. Trevillyan, Hua Xiang
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Patent number: 7913202Abstract: A design structure for a 3D chip having at least one I/O layer connected to other 3D chip layers by a vertical bus such that the I/O layer(s) may accommodate protection and off-chip device drive circuits, customization circuits, translation circuits, conversions circuits and/or built-in self-test circuits capable of comprehensive chip or wafer level testing wherein the I/O layers function as a testhead. Substitution of I/O circuits or structures may be performed using E-fuses or the like responsive to such testing.Type: GrantFiled: November 27, 2007Date of Patent: March 22, 2011Assignee: International Business Machines CorporationInventors: Kerry Bernstein, Paul Coteus, Ibrahim M. Elfadel, Philip Emma, Daniel Friedman, Ruchir Puri, Mark B. Ritter, Jeannine Trewhella, Albert M. Young
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Publication number: 20110004857Abstract: A computer executed method is disclosed which accepts an original circuit with an original logic, accepts a modified circuit, and synthesizes a difference circuit. The difference circuit represents changes that implement the modified circuit's logic for the original circuit. The synthesis may locate an output-side boundary in the original logic in such a manner that the original logic is free of logic changes inbetween the output-side boundary and the primary output elements of the original circuit. The disclosed synthesis may also locate an input-side boundary in the original logic in such a manner that the original logic is free of logic changes inbetween the input-side boundary and the primary input elements of the original circuit. A computer program products are also disclosed. The computer program product contains a computer useable medium having a computer readable program code embodied therein.Type: ApplicationFiled: July 2, 2009Publication date: January 6, 2011Applicant: International Business Machines CorporationInventors: Jeremy T. Hopkins, John M. Isakson, Joachim Keinert, Smita Krishnaswamy, Nilesh A. Modi, Ruchir Puri, Haoxing Ren, David L. Rude
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Publication number: 20100218155Abstract: A method, computer program product, and data processing system for efficiently performing automated placement of timing-critical unit-level cells in a hierarchical integrated circuit design is disclosed. In preparation for global optimization the entire unit at the cell level, macro-level cells are assigned a “placement force” that serves to limit the movement of the macro-level cells from their current position. Movement boundaries for each macro element are also defined, so as to keep the components in a given macro element in relative proximity to each other. Optimization/placement of the unit design is then performed, via a force-directed layout algorithm, on a “flattened” model of the design while respecting the movement boundaries. Following this “flattened” optimization, the placed “unit-level” cells are modeled as blockages and the macro elements are optimized individually, while respecting the location(s) of the blockages.Type: ApplicationFiled: February 26, 2009Publication date: August 26, 2010Inventors: Bruce M. Fleischer, David J. Geiger, Hung C. Ngo, Ruchir Puri, Hoaxing Ren
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Publication number: 20100077372Abstract: Methods, apparatus and computer program products provide a fast and accurate model for simulating the effects of chemical mechanical polishing (CMP) steps during fabrication of an integrated circuit by generating a design of an integrated circuit; while generating the design of the integrated circuit, using a simplified model to predict at least one physical characteristic of the integrated circuit which results from a CMP processing step to be used during manufacture of the integrated circuit, wherein the simplified model is derived from simulations performed prior to the design generation activities using a comprehensive simulation program used to model the physical characteristic; predicting performance of the integrated circuit using the predicted physical characteristic; and adjusting the design of the integrated circuit in dependence on the performance prediction.Type: ApplicationFiled: September 25, 2008Publication date: March 25, 2010Inventors: Hua Xiang, Laertis Economikos, Mohammed F. Fayaz, Stephen E. Greco, Patricia A. O'Neil, Ruchir Puri
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Patent number: 7685553Abstract: An electronic circuit layout refinement method and system. A grid of equally sized tiles is defined on a circuit layout area. Each tile of the grid has a respective critical area estimate metric associated with critical area estimates for a circuit to be placed on the circuit layout area. A global circuit routing for a circuit to be placed within a plurality of tiles of the grid is performed. An estimation of critical area estimate metrics that are assigned to respective tiles of the grid is performed prior to performing a detailed circuit routing for the circuit. The global circuit routing is adjusted, after estimating the critical area estimate metrics, in order to improve a respective critical area estimate metric assigned to at least one tile of the grid. The adjusted global circuit routing is then produced.Type: GrantFiled: April 11, 2007Date of Patent: March 23, 2010Assignee: International Business Machines CorporationInventors: Evanthia Papadopoulou, Ruchir Puri, Mervyn Y. Tan, Louise H. Trevillyan, Hua Xiang
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Patent number: 7676779Abstract: A system for logic block timing analysis may include a controller, and storage in communication with the controller. The storage may provide delay-versus-conesize values of a logic block. The system may further include a fitting module to provide a delay-cone based upon the delay-versus-conesize values of the logic block. The system may also include a conesize parser that uses the delay-cone to provide delay values through the logic block. The conesize parser may be used to validate the design of the logic block by comparing the delay-cone with a desired cycle time.Type: GrantFiled: September 11, 2007Date of Patent: March 9, 2010Assignee: International Business Machines CorporationInventors: Reinaldo A. Bergamaschi, Sean M. Carey, Brian W. Curran, Prabhakar N. Kudva, Matthew E. Mariani, Mark D. Mayo, Ruchir Puri
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Publication number: 20090217227Abstract: In one embodiment, the invention is a method and apparatus for parallel processing of semiconductor chip designs. One embodiment of a method for processing a semiconductor chip design includes flattening a netlist corresponding to the semiconductor chip design, performing logic clustering on one or more logic elements incorporated in the flattened netlist to generate one or more clusters, partitioning the semiconductor chip design in accordance with the one or more clusters, and designing the individual partitions in parallel.Type: ApplicationFiled: February 22, 2008Publication date: August 27, 2009Inventors: MICHAEL W. DOTSON, Anthony DeGroff Drumm, Dazhuang J. Ma, Ruchir Puri, Louise H. Trevillyan
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Publication number: 20090193377Abstract: Power, routability and electromigration have become crucial issues in modem microprocessor designs. In high performance designs, clocks are the highest consumer of power. Arranging clocking components with regularity so as to minimize the capacitance of the clock nets can help reduce clock power, however, it may hurt performance due to some loss of flexibility in physically placing those components. The present invention provides techniques to optimally design a clock network by logically assigning clusters of the latches to respective clock distribution structures, placing clock pins at favored pin locations, and placing clock distribution structures directly underneath the clock pins. The clock distribution structures may be moved to favored distribution locations along the clock stripes, and new optimal clustering generated between the latches and the clock distribution structures. These three optimizations are preferably repeated iteratively to derive a local optimal solution for the clock network.Type: ApplicationFiled: January 30, 2008Publication date: July 30, 2009Inventors: Ruchir Puri, Haifeng Qian, Chin Ngai Sze, James Warnock