Patents by Inventor Rudolf Rothmaler
Rudolf Rothmaler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230282596Abstract: In an embodiment, a semiconductor wafer includes a front surface, a plurality of active component positions, and at least one composite alignment mark arranged on the front surface and indicating a unique orientation of the semiconductor wafer. The composite alignment mark includes a first portion that has at least one raised section formed of a first material and a second portion that is positioned laterally adjacent the first portion. The second portion has at least one raised section formed of a second material that is different form the first material.Type: ApplicationFiled: February 1, 2023Publication date: September 7, 2023Inventors: Andreas Kleinbichler, Daniel Maurer, Joerg Ortner, Rudolf Rothmaler
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Patent number: 11114384Abstract: A power semiconductor die has a semiconductor body, an insulation layer on the semiconductor body, a passivation structure arranged above the insulation layer so as to expose a first insulation layer subsection that extends to an edge of the power semiconductor die, and an interruption structure in the first insulation layer subsection.Type: GrantFiled: October 12, 2018Date of Patent: September 7, 2021Assignee: Infineon Technologies Austria AGInventors: Oliver Blank, Christof Altstaetter, Ingmar Neumann, Rudolf Rothmaler
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Publication number: 20190115302Abstract: A power semiconductor die has a semiconductor body, an insulation layer on the semiconductor body, a passivation structure arranged above the insulation layer so as to expose a first insulation layer subsection that extends to an edge of the power semiconductor die, and an interruption structure in the first insulation layer subsection.Type: ApplicationFiled: October 12, 2018Publication date: April 18, 2019Inventors: Oliver Blank, Christof Altstaetter, Ingmar Neumann, Rudolf Rothmaler
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Patent number: 9923064Abstract: A vertical semiconductor device includes a semiconductor body having a front side, a backside arranged opposite to the front side and a lateral edge delimiting the semiconductor body in a horizontal direction perpendicular to the front side, a gate metallization arranged on the front side and extending at least close to the lateral edge; a contact metallization arranged on the front side and between the lateral edge and the gate metallization, and a backside metallization arranged on the backside and in electric contact with the contact metallization. The gate metallization is arranged around at least two sides of the contact metallization when viewed from above.Type: GrantFiled: November 6, 2015Date of Patent: March 20, 2018Assignee: Infineon Technologies Austria AGInventor: Rudolf Rothmaler
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Patent number: 9704748Abstract: A method of dicing a wafer includes providing a wafer and etching the wafer to singulate die between kerf line segments defined within an interior region of the wafer and to singulate a plurality of wafer edge areas between the kerf line segments and a circumferential edge of the wafer. Each one of the plurality of wafer edge areas is singulated by kerf lines that each extend between one of two endpoints of one of the kerf line segments and the circumferential edge of the wafer.Type: GrantFiled: June 25, 2015Date of Patent: July 11, 2017Assignee: Infineon Technologies AGInventors: Joerg Ortner, Michael Roesner, Gudrun Stranzl, Rudolf Rothmaler
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Publication number: 20160379884Abstract: A method of dicing a wafer includes providing a wafer and etching the wafer to singulate die between kerf line segments defined within an interior region of the wafer and to singulate a plurality of wafer edge areas between the kerf line segments and a circumferential edge of the wafer. Each one of the plurality of wafer edge areas is singulated by kerf lines that each extend between one of two endpoints of one of the kerf line segments and the circumferential edge of the wafer.Type: ApplicationFiled: June 25, 2015Publication date: December 29, 2016Inventors: Joerg Ortner, Michael Roesner, Gudrun Stranzl, Rudolf Rothmaler
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Patent number: 9496339Abstract: A semiconductor device includes a central portion and an edge termination portion outside the central portion. The central portion includes a transistor cell array in a semiconductor substrate. Components of transistor cells of the transistor cell array are disposed in adjacent trench structures in the semiconductor substrate. The trench structures run in a first linear direction parallel to a main surface of the semiconductor substrate. The trench structures include a plurality of concatenated trench segments in a plane parallel to the main surface in the central portion, at least one of the trench segments connecting a first point and a second point of one trench structure, the first point and the second point being arranged along the first linear direction. The trench segment comprises a portion extending in a direction different from the first direction.Type: GrantFiled: June 2, 2014Date of Patent: November 15, 2016Assignee: Infineon Technologies Austria AGInventors: Minghao Jin, Rudolf Rothmaler, Oliver Blank, Joerg Ortner
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Patent number: 9478639Abstract: A method of forming trench electrode structures includes forming a first dielectric layer on a semiconductor substrate, forming a second layer above the first dielectric layer and forming an opening which extends through the second layer and the first dielectric layer to the semiconductor substrate such that part of the semiconductor substrate is uncovered. The method further comprises forming an epitaxial layer on the uncovered part of the semiconductor substrate, removing the second layer after forming the epitaxial layer and filling an open space formed by removing the second layer with an electrically conductive material. The electrically conductive material forms an electrode which is laterally surrounded by the epitaxial layer.Type: GrantFiled: February 27, 2015Date of Patent: October 25, 2016Assignee: Infineon Technologies Austria AGInventors: Minghao Jin, Oliver Blank, Rudolf Rothmaler, Johannes Baumgartl
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Publication number: 20160254367Abstract: A method of forming trench electrode structures includes forming a first dielectric layer on a semiconductor substrate, forming a second layer above the first dielectric layer and forming an opening which extends through the second layer and the first dielectric layer to the semiconductor substrate such that part of the semiconductor substrate is uncovered. The method further comprises forming an epitaxial layer on the uncovered part of the semiconductor substrate, removing the second layer after forming the epitaxial layer and filling an open space formed by removing the second layer with an electrically conductive material. The electrically conductive material forms an electrode which is laterally surrounded by the epitaxial layer.Type: ApplicationFiled: February 27, 2015Publication date: September 1, 2016Inventors: Minghao Jin, Oliver Blank, Rudolf Rothmaler, Johannes Baumgartl
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Publication number: 20160141376Abstract: A vertical semiconductor device includes a semiconductor body having a front side, a backside arranged opposite to the front side and a lateral edge delimiting the semiconductor body in a horizontal direction perpendicular to the front side, a gate metallization arranged on the front side and extending at least close to the lateral edge; a contact metallization arranged on the front side and between the lateral edge and the gate metallization, and a backside metallization arranged on the backside and in electric contact with the contact metallization. The gate metallization is arranged around at least two sides of the contact metallization when viewed from above.Type: ApplicationFiled: November 6, 2015Publication date: May 19, 2016Inventor: Rudolf Rothmaler
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Patent number: 9324823Abstract: A semiconductor device includes a semiconductor body having a first surface vertically spaced apart from a second surface. A first trench vertically extends into the semiconductor body from the first surface and includes first and second sidewalls extending across the semiconductor body in a lateral direction that is parallel to the first surface. A field electrode is arranged in first trench and electrically insulated from the semiconductor body by a field dielectric. A first gate electrode is arranged in the first trench. The first gate electrode is electrically insulated from the field electrode by the field dielectric and is electrically insulated from the semiconductor body by a first gate oxide. The first gate electrode includes widened and tapered portions that are continuously connected and adjacent to one another in the lateral direction. The first gate oxide forms a non-perpendicular angle with the first sidewall in the lateral direction.Type: GrantFiled: August 15, 2014Date of Patent: April 26, 2016Assignee: Infineon Technologies Austria AGInventors: Oliver Blank, Rudolf Rothmaler, Christof Altstaetter, Minghao Jin
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Publication number: 20160049486Abstract: A semiconductor device includes a semiconductor body having a first surface vertically spaced apart from a second surface. A first trench vertically extends into the semiconductor body from the first surface and includes first and second sidewalls extending across the semiconductor body in a lateral direction that is parallel to the first surface. A field electrode is arranged in first trench and electrically insulated from the semiconductor body by a field dielectric. A first gate electrode is arranged in the first trench. The first gate electrode is electrically insulated from the field electrode by the field dielectric and is electrically insulated from the semiconductor body by a first gate oxide. The first gate electrode includes widened and tapered portions that are continuously connected and adjacent to one another in the lateral direction. The first gate oxide forms a non-perpendicular angle with the first sidewall in the lateral direction.Type: ApplicationFiled: August 15, 2014Publication date: February 18, 2016Inventors: Oliver Blank, Rudolf Rothmaler, Christof Altstaetter, Minghao Jin
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Publication number: 20150349056Abstract: A semiconductor device includes a central portion and an edge termination portion outside the central portion. The central portion includes a transistor cell array in a semiconductor substrate. Components of transistor cells of the transistor cell array are disposed in adjacent trench structures in the semiconductor substrate. The trench structures run in a first linear direction parallel to a main surface of the semiconductor substrate. The trench structures include a plurality of concatenated trench segments in a plane parallel to the main surface in the central portion, at least one of the trench segments connecting a first point and a second point of one trench structure, the first point and the second point being arranged along the first linear direction. The trench segment comprises a portion extending in a direction different from the first direction.Type: ApplicationFiled: June 2, 2014Publication date: December 3, 2015Inventors: Minghao Jin, Rudolf Rothmaler, Oliver Blank, Joerg Ortner