Patents by Inventor Ruen-Rone Lee

Ruen-Rone Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020089701
    Abstract: The invention provides a method and an apparatus for dithering, and inversely dithering an image. The apparatus makes use of a pixel address and a pixel data to locate a dither reference value from a dither matrix and use the dither reference value to convert an original pixel data having N bits into a dithered pixel data having M bits (N>M). On the other hand, the apparatus for performing an inversely dithering process makes use of the pixel address and the dithered pixel data (M bits) to locate a dither reference value from a dither matrix. Then, the dither reference value is employed to perform an inversely dithering process to recover the dithered pixel data into original pixel data.
    Type: Application
    Filed: July 24, 2001
    Publication date: July 11, 2002
    Inventors: Chung-Yen Lu, Ruen-rone Lee
  • Patent number: 6377273
    Abstract: A pixel based method for the computation of sub-pixel area-coverage is implemented in an area-coverage hardware module, within a 3D computer graphics rendering engine. Unlike the prior art segment based method which requires an operating aperture of an entire segment, the present invention only requires an operating aperture of one pixel. Therefore, the overall system pixel yield rate is increased.
    Type: Grant
    Filed: November 4, 1998
    Date of Patent: April 23, 2002
    Assignee: Industrial Technology Research Institute
    Inventors: Ruen-Rone Lee, Shin-Ping Robert Wang, Kuo-Chang Fu
  • Patent number: 6057861
    Abstract: A linear address organization for physically storing mip maps and rip maps in memory is disclosed. The subsampled data arrays of the mip maps and rip maps are sequentially stored in continuous subsequences of a continuous sequence of memory addresses. The subsequences of addresses are assigned in order of level of subsampling of the data arrays which make up the mip map or rip map. In the case of a mip map, the subsequences are assigned to the data arrays in order of increasing level of subsampling. In the case of rip maps, the data arrays are segregated into groups according to a first one of the two subsampling directions, such that each array in a particular group has the same level of subsampling in the first direction. Subsequences are assigned to each group of data arrays.
    Type: Grant
    Filed: June 2, 1999
    Date of Patent: May 2, 2000
    Assignee: Industrial Technology Research Institute
    Inventors: Ruen-Rone Lee, Chun-Kai Huang, Wei-Kuo Chia
  • Patent number: 5963220
    Abstract: A linear address organization for physically storing mip maps and rip maps in memory is disclosed. The subsampled data arrays of the mip maps and rip maps are sequentially stored in continuous subsequences of a continuous sequence of memory addresses. The subsequences of addresses are assigned in order of level of subsampling of the data arrays which make up the mip map or rip map. In the case of a mip map, the subsequences are assigned to the data arrays in order of increasing level of subsampling. In the case of rip maps, the data arrays are segregated into groups according to a first one of the two subsampling directions, such that each array in a particular group has the same level of subsampling in the first direction. Subsequences are assigned to each group of data arrays.
    Type: Grant
    Filed: February 8, 1996
    Date of Patent: October 5, 1999
    Assignee: Industrial Technology Research Institute
    Inventors: Ruen-Rone Lee, Chun-Kai Huang, Wei-Kuo Chia
  • Patent number: 5946005
    Abstract: Disclosed is an improved computer graphics memory architecture. The architecture includes an address translation table (ATT) and a buffer. The address translation table receives information about desired pixel data and determines the physical address of the desired data. The buffer is connected to the ATT and has a dual bank which stores the color value and the Z value of a 3-D pixel. A buffer addressing method is also provided in which the address of the desired pixel information and associated control circuits may be quickly determined through an appropriate data arrangement in the buffer and an address transfer table.
    Type: Grant
    Filed: August 27, 1997
    Date of Patent: August 31, 1999
    Assignee: Industrial Technology Research Institute
    Inventors: Ming-Mao Chiang, Ruen-Rone Lee, Ming-Fen Lin
  • Patent number: 5751290
    Abstract: A method and system are provided for drawing one or more surfaces. The system includes a drawing processor, a frame buffer with z buffer and a display device, such as a display monitor. The drawing processor can perform all of the following steps. A first pixel in a first row is selected. The first pixel is near a first point at which a projection onto a plane of view of a first edge of a first surface intersects the first row of pixels in the plane of view. A first distance from the first point to a second point on the first surface is determined. The first point is a projection onto the plane of view of the second point. The first distance is then corrected by a first value representing a difference in distance between the first distance and a distance from the first pixel to a third point on the first surface. The first pixel overlies, e.g., and is centered at, a point that is a projection onto the plane of view of the third point.
    Type: Grant
    Filed: September 20, 1996
    Date of Patent: May 12, 1998
    Assignee: Industrial Technology Research Institute
    Inventors: Ruen-Rone Lee, Chun-Kai Huang