Patents by Inventor Ruey-Hsin Lin

Ruey-Hsin Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • High voltage transistor using P+ buried layer
    Patent number: 6423590
    Abstract: A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This allows much higher breakdown voltages to be achieved. In particular, the device will not break down at the bottom of the base-collector junction which is the weak spot for conventional devices. A process for manufacturing this device is described. A particular feature of this new process is that the N type epitaxial layer that is grown over the P+ layer is only about half the thickness of its counterpart in the conventional device. The process is fully compatible with conventional BiCMOS processes and has lower cost.
    Type: Grant
    Filed: May 2, 2001
    Date of Patent: July 23, 2002
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Jun-Lin Tsai, Ruey-Hsin Lin, Jei-Feng Hwang, Kuo-Chio Liu
  • High voltage transistor using P+ buried layer
    Publication number: 20010017379
    Abstract: A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This allows much higher breakdown voltages to be achieved. In particular, the device will not break down at the bottom of the base-collector junction which is the weak spot for conventional devices. A process for manufacturing this device is described. A particular feature of this new process is that the N type epitaxial layer that is grown over the P+ layer is only about half the thickness of its counterpart in the conventional device. The process is fully compatible with conventional BiCMOS processes and has lower cost.
    Type: Application
    Filed: May 2, 2001
    Publication date: August 30, 2001
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY
    Inventors: Jun-Lin Tsai, Ruey-Hsin Lin, Jei-Feng Hwang, Kuo-Chio Liu