Abstract: A method for making an improved polysilicon emitter for a bipolar transistor in a BiCMOS integrated circuit is achieved. The method uses a novel stacked undoped amorphous silicon layer and a doped polysilicon layer. The polysilicon layer is doped by ion implantation while the amorphous silicon layer remains undoped. The stacked layer is patterned to form a polysilicon emitter source over the bipolar transistor, while concurrently forming gate electrodes for the FETs. The undoped amorphous silicon layer retards the diffusion from the doped polysilicon to provide a shallower emitter junction during subsequent thermal processing. At a later step a rapid thermal anneal (RTA) is carried out in which the amorphous silicon layer provides better control of the diffused emitter depth (junction) while concurrently activating the implant dopant in the FET source/drain areas.

Abstract: The device includes a N+ buried layer in a substrate. A P-well is formed in an epitaxial layer on the buried layer. N-wells surround the P-well are also formed in the epitaxial layer. One of the N-well regions acts as a drain in the structure. A plurality of field oxide regions is formed on the N-well or P-well to define the active area of the device. A gate oxide is formed on the surface of the P-well and the N-well served as the drain. A gate is formed on the gate oxide. Drain contact is formed in the N-well for drain. The source region of the device is formed in the P-well adjacent to the drain. An isolation layer is deposited on the gate. The method includes forming a N+ buried layer in a P substrate. A P epitaxial layer is then formed on the surface of the P substrate. The N-well and P-well are respectively formed in the epitaxial layer by ion implantation and thermally diffusion. A plurality of field oxide (FOX) regions are created to define the active area.

Abstract: A method for fabricating a buried layer pinched collector bipolar, (BPCB), device, sharing several process steps with simultaneously formed CMOS devices, has been developed. The BPCB device fabrication sequence features the use of polysilicon field plates,. placed on field oxide regions, in an area of an N well region in which the field oxide regions are located between subsequent P type, base and N type, collector regions. The use of the polysilicon field plates results in an increase in collector—emitter breakdown voltage, as a result of a reduction in the electric field at the surface underlying the polysilicon field plates.

Abstract: A method for fabricating a buried layer pinched collector bipolar, (BPCB), device, sharing several process steps with simultaneously formed CMOS devices, has been developed. The BPCB device fabrication sequence features the use of field ring regions, placed in an N well region, and located between a base and collector region. The use of the field ring results in an increase in collector-emitter breakdown voltage, as a result of the reduction in local dopant concentration in the N well region. This phenomena, the reduction the local dopant concentration in the N well region, in the vicinity of the field ring region, allows a higher N well dopant concentration to be used, resulting in increased frequency responses, (Ft), of the BPCB device, when compared to counterparts fabricated without the field ring regions, and thus with a lower N well dopant concentration.

Abstract: A method of forming a semiconductor device includes forming of layers of polysilicon and dielectric layers in manufacturing a semiconductor device and patterning the layers into devices using phototlithography and etching process steps. End point mode detection is used in the etching process in a way in which the area exposed during etching is increased to enhance the end point detection capacity, by adding a surplus pad area before pad formation. Specifically an EPROM device is formed with a first level of polysilicon above a gate oxide layer patterned into a floating gate electrode of an EPROM device. Then form an ONO layer above the floating gate electrode. Define array protection, grow a second gate oxide layer, deposit a second level of polysilicon, define peripheral gates from the second level of polysilicon, and define an EPROM transistor gate electrode from the second level of polysilicon.