Abstract: An object of the present invention is to provide an external use composition having a novel composition that has a superior effect promoting collagen production and is able to suppress, prevent or improve wrinkles and sagging of the skin with aging. The present invention relates to an external use composition for anti-aging, comprising (A) a lipopeptide represented by the following formula (1), or a pharmaceutically acceptable salt thereof: (wherein, R1 represents a saturated aliphatic group, or aliphatic group having a single unsaturated bond, having 9 to 19 carbon atoms, and m represents 0 or 1).

Abstract: An object of the present invention is to provide an external use composition having a novel composition that has a superior effect promoting collagen production and is able to suppress, prevent or improve wrinkles and sagging of the skin with aging. The present invention relates to an external use composition for anti-aging, comprising (A) a lipopeptide represented by the following formula (1), or a pharmaceutically acceptable salt thereof: (wherein, R1 represents a saturated aliphatic group, or aliphatic group having a single unsaturated bond, having 9 to 19 carbon atoms, and m represents 0 or 1).

Abstract: A microcomputer includes a register that stores division ratio setting information, a frequency divider that determines first and second division ratios based on the division ratio setting information, frequency-divides a first clock having a first frequency at the first division ratio, and frequency-divides a second clock having a second frequency at the second division ratio, and a CPU. The first and second division ratios are determined in such a manner that a frequency of the first clock that is frequency-divided at the first division ratio and a frequency of the second clock that is frequency-divided at the second division ratio are made equal to each other.

Abstract: A microcomputer includes a register that stores division ratio setting information, a frequency divider that determines first and second division ratios based on the division ratio setting information, frequency-divides a first clock having a first frequency at the first division ratio, and frequency-divides a second clock having a second frequency at the second division ratio, and a CPU. The first and second division ratios are determined in such a manner that a frequency of the first clock that is frequency-divided at the first division ratio and a frequency of the second clock that is frequency-divided at the second division ratio are made equal to each other.

Abstract: A voltage detection circuit including a voltage selection circuit that outputs a voltage commensurate with a power supply voltage as a first voltage; a detection voltage selection circuit that selects either an external input voltage inputted from an external terminal or the first voltage according to a first control signal, and outputs it as a comparison voltage; a reference voltage generation circuit that generates a reference voltage; a comparator that compares the reference voltage and the comparison voltage, and outputs the comparison result as a detection signal; a control circuit that generates the first control signal so that the detection voltage selection circuit may output either the first voltage or the external input voltage as the comparison voltage by time division, and when a variation of the first voltage is detected, generates the first control signal so that the detection object selection circuit may output the first voltage as the comparison voltage.

Abstract: A clock generation circuit includes a system clock selection circuit that selects one of a first and a second clock signals with different frequencies from each other as a system clock signal according to a selection signal, a frequency division circuit that divides the system clock signal and generates a plurality of divided clock signals, and a communication clock selection circuit that selects a communication clock signal from the plurality of divided clock signals according to the selection signal and a division ratio setting signal, and switches to the selected communication clock signal in synchronization with a switching timing of the selection signal.

Abstract: A clock generation circuit includes a system clock selection circuit that selects one of a first and a second clock signals with different frequencies from each other as a system clock signal according to a selection signal, a frequency division circuit that divides the system clock signal and generates a plurality of divided clock signals, and a communication clock selection circuit that selects a communication clock signal from the plurality of divided clock signals according to the selection signal and a division ratio setting signal, and switches to the selected communication clock signal in synchronization with a switching timing of the selection signal.

Abstract: A voltage detection circuit including a voltage selection circuit that outputs a voltage commensurate with a power supply voltage as a first voltage; a detection voltage selection circuit that selects either an external input voltage inputted from an external terminal or the first voltage according to a first control signal, and outputs it as a comparison voltage; a reference voltage generation circuit that generates a reference voltage; a comparator that compares the reference voltage and the comparison voltage, and outputs the comparison result as a detection signal; a control circuit that generates the first control signal so that the detection voltage selection circuit may output either the first voltage or the external input voltage as the comparison voltage by time division, and when a variation of the first voltage is detected, generates the first control signal so that the detection object selection circuit may output the first voltage as the comparison voltage.

Abstract: An oscillating section 110 comprised of feedback inverter INV1 and a feedback resistor R2, and a waveform shaping section 120 including a Schmitt circuit S1 of which transistors P3 and N3 respectively receive, as gate control signals, signals Gp3 and Gn3 generated by a stable-oscillation signal A1 and logic elements AND1, OR1 and INV3, respectively, and the supply of power to the waveform shaping section 120 is performed through a low pass filter 111 comprised of a resistor R1 and a capacitor C1 and thus a high potential power source VDD is supplied to the waveform shaping section 120 as a high potential power source VDDX.

Abstract: An oscillating section 110 comprised of feedback inverter INV1 and a feedback resistor R2, and a waveform shaping section 120 including a Schmitt circuit S1 of which transistors P3 and N3 respectively receive, as gate control signals, signals Gp3 and Gn3 generated by a stable-oscillation signal A1 and logic elements AND1, OR1 and INV3, respectively, and the supply of power to the waveform shaping section 120 is performed through a low pass filter 111 comprised of a resistor R1 and a capacitor C1 and thus a high potential power source VDD is supplied to the waveform shaping section 120 as a high potential power source VDDX.

Abstract: A reading defect detecting circuit of EEPROM is provided. An ordinary read voltage generating circuit generates a read voltage V1, and a defect detecting read voltage generating circuit generates a defect detecting read voltage V2 which is slightly higher than the voltage V1. A selector selects the voltage V1 or V2 to apply it to a FLASH EEPROM, and the data are read out from a FLASH EEPROM. Both data being readout at voltage V1 and voltage V2 are compared in a comparator. If the data are not matched, an error flag is generated in the comparator, and it is used as an interrupt signal, thereby the CPU recognizes the error. The mismatched address and correct data at this address are read out, and thereby the correct data is written again at the mismatched address.