Abstract: A circuit arrangement for generating the clock signal of a predetermined frequency f(UART) for a smart card interface, the interface being used for transferring data from a smart card to a device e.g. a mobile telephone at a predetermined data rate f(D). Using a phase-locked loop (PLL) and a number of programmable counters (N1-N4), the output of the circuit i.e. the smart card interface clock signal can have a frequency f(UART) which is a multiple of the data rate. In particular, the counters (N1-N4) and phase-locked loop (PLL) can be chosen so that f(UART) is sixteen times f(D) which allows a Universal Asynchronous Receiver Transmitter circuit to be used in the interface.

Abstract: A divider circuit provides an output signal having a frequency which is equal to the frequency of an input signal divided by an odd integer. This is achieved by feeding back the output from a binary counter through an AND gate, delay flip-flop and an OR gate so that one cycle is added the output of the binary counter.

Abstract: The power consumption of an electrical device can be optimised by altering the clock frequency of circuits (MCU, 1-3) in the device which are controlled by a clock signal. The state and need for processing power of the circuits (MCU, 1-3) or blocks (21-23) in the circuits (2) is supervised, and the clock frequency of the circuit (MCU, 1-3) or block (21-23) in the device is changed according to the need for processing power. The appropriate clock frequency is selected from one of a plurality of clock signals (clk(1) . . . clk(n)), input to a selection circuit which is then coupled to the output of the selection circuit for use as the clock for the circuit.