Abstract: An approach for representing integrated circuit device characteristics using polynomial equations involves analyzing integrated circuit device characterization data in a lookup table form and using an order incremental scheme to determine a polynomial equation of a relatively low-order that satisfies specified accuracy criteria. In situations where a polynomial equation that has an order less than a maximum allowable order cannot be determined, the integrated circuit device characterization data is partitioned into sub-domains and polynomial equations are determined separately for each sub-domain. The separate polynomial equations are then combined to generate a piecewise polynomial equation that represents all of the integrated circuit device characterization data.

Abstract: An approach for reducing antenna effects in integrated circuits involves evaluating an integrated circuit design to identify one or more problem interconnects that satisfy certain antenna effect criteria. The problem interconnects are selectively connected to one or more discharge paths and the integrated circuit design is updated to reflect the connections to the one or more discharge paths.

Abstract: A user-programmable gate array architecture includes an array of logic function modules which may comprise one or more combinatorial and/or sequential logic circuits. An interconnect architecture comprising a plurality of horizontal and vertical general interconnect channels, each including a plurality of interconnect conductors some of which may be segmented, is imposed on the array. Individual ones of the interconnect conductors are connectable to each other and to the inputs and outputs of the logic function modules by user-programmable interconnect elements. A local interconnect architecture comprising local interconnect channels is also imposed on the array. Each local interconnect channel includes a plurality of local interconnect conductors and runs between pairs of adjacent ones of the logic function modules.

Abstract: A user-programmable gate array architecture includes an array of logic function modules which may comprise one or more combinatorial and/or sequential logic circuits. An interconnect architecture comprising a plurality of horizontal and vertical general interconnect channels, each including a plurality of interconnect conductors some of which may be segmented, is imposed on the array. Individual ones of the interconnect conductors are connectable to each other and to the inputs and outputs of the logic function modules by user-programmable interconnect elements. A local interconnect architecture comprising local interconnect channels is also imposed on the array. Each local interconnect channel includes a plurality of local interconnect conductors and runs between pairs of adjacent ones of the logic function modules.

Abstract: A user-programmable gate array architecture includes an array of logic function modules which may comprise one or more combinatorial and/or sequential logic circuits. An interconnect architecture comprising a plurality of horizontal and vertical general interconnect channels, each including a plurality of interconnect conductors some of which may be segmented, is imposed on the array. Individual ones of the interconnect conductors are connectable to each other and to the inputs and outputs of the logic function modules by user-programmable interconnect elements. A local interconnect architecture comprising local interconnect channels is also imposed on the array. Each local interconnect channel includes a plurality of local interconnect conductors and runs between pairs of adjacent ones of the logic function modules.