Abstract: A method for large scene elastic semantic representation and self-supervised light field reconstruction is provided. The method includes acquiring a first depth map set corresponding to a target scene, in which the first depth map set includes a first depth map corresponding to at least one 5 angle of view; inputting the first depth map set into a target elastic semantic reconstruction model to obtain a second depth map set, in which the second depth map set includes a second depth map corresponding to the at least one angle of view; and fusing the second depth map corresponding to the at least one angle of view to obtain a target scene point cloud corresponding to the target scene.

Abstract: A wiring substrate includes wiring layers and insulation layers alternately stacked. Via holes are formed in the insulation layers. First via wirings are formed in the via holes to electrically connect the wiring layers to one another. Through holes extend through a lowermost one of the insulation layers in a thickness direction. The lowermost insulation layer covers a lowermost one of the wiring layers. Second via wirings are formed in the through holes to define an identification mark that is identifiable as a specific shape including a character, a symbol, or a combination thereof. A lower surface of each of the second via wirings is exposed from a lower surface of the lowermost insulation layer and is flush with a lower surface of the lowermost wiring layer.

Abstract: A wiring substrate includes an insulating layer, a pad, and a solder resist layer. The insulating layer has a first surface formed with a first recess portion. The pad is embedded in the first recess portion. The pad includes a second surface and a third surface. The third surface that is located at a lower position than the first surface so as to expose an inner wall surface of the first recess portion. The pad is formed with a second recess portion in a center portion of the third surface. The solder resist layer is provided on the first surface. An adjacent portion of the first surface to a peripheral portion of the first recess portion is smaller in roughness than a region of the first surface peripheral to the adjacent portion of the first surface.

Abstract: A wiring substrate includes wiring layers and insulation layers alternately stacked. Via holes are formed in the insulation layers. First via wirings are formed in the via holes to electrically connect the wiring layers to one another. Through holes extend through a lowermost one of the insulation layers in a thickness direction. The lowermost insulation layer covers a lowermost one of the wiring layers. Second via wirings are formed in the through holes to define an identification mark that is identifiable as a specific shape including a character, a symbol, or a combination thereof. A lower surface of each of the second via wirings is exposed from a lower surface of the lowermost insulation layer and is flush with a lower surface of the lowermost wiring layer.

Abstract: A wiring substrate includes an insulating layer, a pad, and a solder resist layer. The insulating layer has a first surface formed with a first recess portion. The pad is embedded in the first recess portion. The pad includes a second surface and a third surface. The third surface that is located at a lower position than the first surface so as to expose an inner wall surface of the first recess portion. The pad is formed with a second recess portion in a center portion of the third surface. The solder resist layer is provided on the first surface. An adjacent portion of the first surface to a peripheral portion of the first recess portion is smaller in roughness than a region of the first surface peripheral to the adjacent portion of the first surface.