Abstract: A voltage regulator circuit includes a switch device that is coupled between an input power supply and a regulated power supply node. The voltage regulator circuit adjusts a value of a current flowing from the input power supply to the regulated power supply node by modifying a voltage level of a control node coupled to the switch device. A control circuit adjusts the voltage level of the control node using an error signal based on a comparison of the voltage level of the regulated power supply node and a reference voltage. To improve the response time of the voltage regulator circuit to changes in load current, the control circuit additionally sources current to and/or sinks current from the control node based on a voltage level of the control node.

Abstract: A voltage regulator circuit includes a switch device that is coupled between an input power supply and a regulated power supply node. The voltage regulator circuit adjusts a value of a current flowing from the input power supply to the regulated power supply node by modifying a voltage level of a control node coupled to the switch device. A control circuit adjusts the voltage level of the control node using an error signal based on a comparison of the voltage level of the regulated power supply node and a reference voltage. To improve the response time of the voltage regulator circuit to changes in load current, the control circuit additionally sources current to and/or sinks current from the control node based on a voltage level of the control node.

Abstract: A level shifter circuit with an intermediate power domain and method for operating the same is disclosed. The level shifter circuit includes an input circuit, an output circuit, and an intermediate circuit. The input circuit is coupled to receive an input signal from a first voltage domain operating according to a first supply voltage, and generates a first intermediate signal. The intermediate circuit receives the first intermediate signal and generates a second intermediate signal. The output circuit receives the intermediate signal and provides an output signal into a second voltage domain operating at a second supply voltage different from the first. A voltage multiplexer is configured to provide one of the first or second supply voltages to the intermediate circuit depending on a state of the input signal.

Abstract: A level shifter circuit with an intermediate power domain and method for operating the same is disclosed. The level shifter circuit includes an input circuit, an output circuit, and an intermediate circuit. The input circuit is coupled to receive an input signal from a first voltage domain operating according to a first supply voltage, and generates a first intermediate signal. The intermediate circuit receives the first intermediate signal and generates a second intermediate signal. The output circuit receives the intermediate signal and provides an output signal into a second voltage domain operating at a second supply voltage different from the first. A voltage multiplexer is configured to provide one of the first or second supply voltages to the intermediate circuit depending on a state of the input signal.

Abstract: A voltage regulator circuit includes a comparator configured to compare whether an output voltage of the voltage regulator circuit is either equal to or less than a reference voltage; a control unit, coupled to the comparator, and configured to use a duty ratio of the output voltage to an input voltage of the control unit to estimate a time period; a first transistor, coupled to the control unit, and configured to be selectively turned on based on the estimated time period; and an inductor, coupled to the first transistor, configured to conduct an inductor current, wherein when the comparator determines that the output voltage is either equal to or less than the reference voltage, the first transistor is turned on during the estimated time period to allow the inductor current to be increased so as to accordingly increase the output voltage.

Abstract: A voltage regulator having a pre-regulator circuit is disclosed. A low dropout (LDO) voltage regulator includes an amplifier circuit, a current buffer circuit, and a pre-regulator circuit. The current buffer circuit includes a transistor having a gate terminal coupled to the amplifier output. The current buffer provides a current based at least in part on the output signal generated by the amplifier. The pre-regulator circuit is coupled to provide a dynamic supply voltage to the current buffer. They dynamic supply voltage depends at least in part on a fixed supply voltage provided thereto, as well as the output voltage provided by the LDO voltage regulator.

Abstract: A digital watermarking system and method are disclosed. In one respect, the disclosed digital watermarking includes generating an extracted signal by applying a watermark extractor to an original image, generating a mixed signal by mixing the first signal with a periodic watermark signal using a local weighting factor for the periodic watermark signal that attenuates a strength of the watermark signal in proportion to a pixel luminance level, and replacing the extracted signal in the original image with the mixed signal to generate a marked image, wherein the watermark signal is extractable from the marked image using the watermark extractor.

Abstract: Methods, systems and devices for securely transferring digital data from a first repository to a second repository are disclosed. Per at least one embodiment, a second repository is identified with a human recognizable identifier and an internal identifier associated with such second repository is determined. When a data transfer is desired, a work order associating the data to be transferred and identifying the second repository based on each of the human identifier and the internal identifier is generated. Such work order is utilized by a data port device to open normally closed communications port to accomplish the transfer of the data to the second repository when the identity of such second repository is confirmed by the data port device. A data integrity check confirms that only the designated to be transferred data was actually transferred to the second repository designated in the work order.

Abstract: The present disclosure relates to voltage regulation techniques. In some embodiments, a voltage regulator is configured to regulate an output voltage based on a reference voltage. The voltage regulator comprises an analog-to-digital converter, an encoder, a decoder and a power stage. The analog-to-digital converter receives the reference voltage and an output voltage of the voltage regulator and provides a digital error signal. The encoder is coupled to the analog-to-digital converter output and configured to provide a multi-bit digital control signal based upon a present value of the digital error signal, a plurality of pre-determined coefficients, and a plurality of previous values of the digital error signal. The decoder is coupled to the encoder and configured to generate a plurality of control signals based on the multi-bit digital control signal. The power stage comprises a plurality of power cells which are coupled to a power supply and which receive the plurality of control signals, respectively.

Abstract: Methods, systems and devices for securely transferring digital data from a first repository to a second repository are disclosed. Per at least one embodiment, a second repository is identified with a human recognizable identifier and an internal identifier associated with such second repository is determined. When a data transfer is desired, a work order associating the data to be transferred and identifying the second repository based on each of the human identifier and the internal identifier is generated. Such work order is utilized by a data port device to open normally closed communications port to accomplish the transfer of the data to the second repository when the identity of such second repository is confirmed by the data port device. A data integrity check confirms that only the designated to be transferred data was actually transferred to the second repository designated in the work order.

Abstract: A voltage regulator circuit includes a comparator configured to compare whether an output voltage of the voltage regulator circuit is either equal to or less than a reference voltage; a control unit, coupled to the comparator, and configured to use a duty ratio of the output voltage to an input voltage of the control unit to estimate a time period; a first transistor, coupled to the control unit, and configured to be selectively turned on based on the estimated time period; and an inductor, coupled to the first transistor, configured to conduct an inductor current, wherein when the comparator determines that the output voltage is either equal to or less than the reference voltage, the first transistor is turned on during the estimated time period to allow the inductor current to be increased so as to accordingly increase the output voltage.

Abstract: A voltage regulator circuit includes: a comparator configured to have a first input coupled to an output voltage of the voltage regulator circuit; a second input coupled to a reference voltage and an output signal; a first transistor; a second transistor, a drain of the first transistor connected to a drain of the second transistor; an inductor connected to the drain of the first transistor and the drain of the second transistor; a capacitor and a resistor connected in parallel, between the output node and a source of the second transistor; a peak-current detector unit configured to detect peak current in the inductor; a zero-crossing detector unit configured to detect a zero-crossing current in the inductor; and a control unit configured to receive a plurality of input signals including at least an input voltage and a clock signal.

Abstract: A voltage regulator circuit includes: a comparator configured to have a first input coupled to an output voltage of the voltage regulator circuit; a second input coupled to a reference voltage and an output signal; a first transistor; a second transistor, a drain of the first transistor connected to a drain of the second transistor; an inductor connected to the drain of the first transistor and the drain of the second transistor; a capacitor and a resistor connected in parallel, between the output node and a source of the second transistor; a peak-current detector unit configured to detect peak current in the inductor; a zero-crossing detector unit configured to detect a zero-crossing current in the inductor; and a control unit configured to receive a plurality of input signals including at least an input voltage and a clock signal.

Abstract: The present disclosure relates to voltage regulation techniques. In some embodiments, a voltage regulator is configured to regulate an output voltage based on a reference voltage. The voltage regulator comprises an analog-to-digital converter, an encoder, a decoder and a power stage. The analog-to-digital converter receives the reference voltage and an output voltage of the voltage regulator and provides a digital error signal. The encoder is coupled to the analog-to-digital converter output and configured to provide a multi-bit digital control signal based upon a present value of the digital error signal, a plurality of pre-determined coefficients, and a plurality of previous values of the digital error signal. The decoder is coupled to the encoder and configured to generate a plurality of control signals based on the multi-bit digital control signal. The power stage comprises a plurality of power cells which are coupled to a power supply and which receive the plurality of control signals, respectively.

Abstract: A digital watermarking system and method are disclosed. In one respect, the disclosed digital watermarking includes generating an extracted signal by applying a watermark extractor to an original image, generating a mixed signal by mixing the first signal with a periodic watermark signal using a local weighing factor for the periodic watermark signal that attenuates a strength of the watermark signal in proportion to a pixel luminance level, and replacing the extracted signal in the original image with the mixed signal to generate a marked image, wherein the watermark signal is extractable from the marked image using the watermark extractor.

Abstract: A pulse width modulation (PWM) amplifier includes a first amplifier stage, a second amplifier stage, and a gain module. The first amplifier stage is configured to amplify an analog input signal in the analog and digital domains using a first pulse width modulation (PWM) generator, to provide a first stage output for coupling to a load. The gain module is configured to amplify a quantization error of the first PWM generator by a predetermined gain. The second amplifier stage is configured to spectrally shape and attenuate the amplified quantization error of the first PWM generator using a second PWM generator, to provide a second stage output for coupling to the load.

Abstract: A pulse width modulation (PWM) amplifier includes a first amplifier stage, a second amplifier stage, and a gain module. The first amplifier stage is configured to amplify an analog input signal in the analog and digital domains using a first pulse width modulation (PWM) generator, to provide a first stage output for coupling to a load. The gain module is configured to amplify a quantization error of the first PWM generator by a predetermined gain. The second amplifier stage is configured to spectrally shape and attenuate the amplified quantization error of the first PWM generator using a second PWM generator, to provide a second stage output for coupling to the load.

Abstract: A pulse width modulation (PWM) amplifier includes a first amplifier stage, a second amplifier stage, and a gain module. The first amplifier stage is configured to amplify an analog input signal in the analog and digital domains using a first pulse width modulation (PWM) generator, to provide a first stage output for coupling to a load. The gain module is configured to amplify a quantization error of the first PWM generator by a predetermined gain. The second amplifier stage is configured to spectrally shape and attenuate the amplified quantization error of the first PWM generator using a second PWM generator, to provide a second stage output for coupling to the load.

Abstract: An amplifier includes a first stage, a second stage coupled to the first stage, and a summation circuit. The first stage is configured to receive an analog input signal, convert the analog input signal to a digital signal, and output an intermediate analog output signal in response to the digital signal. The second stage is configured to output a second analog intermediate output signal based on a scaled pulse width modulation quantization error of the first stage. The summation circuit is configured to combine the first and second analog intermediate output signals to generate an amplified output signal.

Abstract: An amplifier includes a first stage, a second stage coupled to the first stage, and a summation circuit. The first stage is configured to receive an analog input signal, convert the analog input signal to a digital signal, and output an intermediate analog output signal in response to the digital signal. The second stage is configured to output a second analog intermediate output signal based on a scaled pulse width modulation quantization error of the first stage. The summation circuit is configured to combine the first and second analog intermediate output signals to generate an amplified output signal.