Abstract: A mechanism that enables multiple Mobile Devices to operate in clusters is provided. Using the mobile cluster mechanism framework provided in this invention, Mobile Devices can execute compute intensive tasks in the field by sharing the task between various devices. The invention also contemplates various options of implementing the cluster mechanism on Mobile Devices. The invention further contemplates solutions for the roaming of Mobile Devices.

Abstract: A mechanism that enables multiple Mobile Devices to operate in clusters is provided. Using the mobile cluster mechanism framework provided in this invention, Mobile Devices can execute compute intensive tasks in the field by sharing the task between various devices. The invention also contemplates various options of implementing the cluster mechanism on Mobile Devices. The invention further contemplates solutions for the roaming of Mobile Devices.

Abstract: A mechanism to generate clocks when there is no security breach is contemplated. Using the conditional generation of clocks for synchronous digital designs, the invention enables mechanisms to secure Mobile Devices. When a potential security breach is detected, clock generation to at least a portion of the Mobile Device is disabled. The invention also contemplates mechanisms to re-enable the Mobile Device when the security risk is resolved.

Abstract: A system and method of authenticating a user of a data network which inserts control information into certain data packets being sent over the network. The control information is user-specific, including such items as user identity, password, originating CPU, or biometric information. Inserting the control information into data packets transmitted during the entire session permits continuous authentication.

Abstract: A system and method of providing secure communications between two or more hosts connected to a public network, where a secure virtual network (SVN) is established among the two or more hosts.

Abstract: A mechanism to secure a synchronous digital device such as a Mobile Device is provided. Using the clocking mechanisms of the synchronous digital designs, the invention enables mechanisms to secure Mobile devices. When a potential security breach is detected, blocking the clock will disable the Mobile Device. The invention also contemplates mechanisms to re-enable the Mobile Device when the security risk from the block condition is resolved. The invention further contemplates mechanisms to secure the enterprise information technology system from the hacked or stolen Mobile Devices.

Abstract: An architecture, system, and method are provided for transparently mapping a network identification number of a host to an access point of an internet. The host can be moved from a first point to a second point on the internet without having to reconfigure routing tables or to update routing protocols. The network identification number of the host does not change as it is moved from the first point to the second point. Thus, the network identification number of the host does not perform routing. Instead, routing occurs by targeting the exit end module onto which the host is connected, i.e., at the second point. The exit end module thereby contains configuration registers which store mapping tables that note the new destination address of any data being sent to the new host location, and properties such as security and priority codes.

Abstract: An architecture, system and method are provided for efficiently transferring packets of data across a communication network. Portions of the communication network is structured such that there are hierarchical levels of high speed Routing Switches existing throughout the network. Distributed routing of packets is achieved by comparing identification numbers of Routing Switches with the destination address of a data packet. Once routing is achieved within the transport ID based network, transfer to a destination termination device occurs through a single look-up table only when departing the network. The routing operation between termination devices can therefore be achieved using a single mapping operation and is backward compatible with devices external to the network and protocols used by those devices.

Abstract: A packet architecture, communication system, and method are provided for determining the location at which a network is disrupted, disabled, and/or severed. The packet can contain control bits and error identification bits which note the location at which disturbance exists, and informs the originating module to take alternative path if necessary. The alternative path can be applied to either re-sending the existing packet or sending future packets between certain modules connected to the network, wherein the network preferably includes one or more ring topologies interconnected with one another between termination devices. The termination devices allow communication across subnets which form an intranet or across a global system, or internet. Although redundant transmission channels are used, each transmission channel preferably does not send redundant packets, nor are the transmission channels dedicated as uni-directional.

Abstract: An architecture, system and method are provided for transparently mapping addresses across multiple addressing domains and/or protocols. A destination of a packet can therefore be transferred from a first addressing domain within one network to a second addressing domain within another network, without inserting knowledge into the packet of the relationship between the two separate and independent domains. Transmission modules within one network can be identified with unique identification numbers or addresses assigned during configuration of those modules. The identification numbers assigned internal to the network can be mapped and placed upon the packet as the packet enters the network. Mapping, however, is minimal, knowing that relatively few external devices are connected to select internal devices and/or modules. The packet can then be mapped into the network, where it is then transferred across the network whereupon it is mapped to another network or termination device external to the network.

Abstract: An architecture, system and method are provided for efficiently transferring packets of data across a communication network. The communication network is structured such that there are hierarchical levels of high speed switches existing throughout the network. Distributed routing of packets is achieved by comparing identification numbers of only select switches with the destination address on a field-by-field basis. Not all fields need be compared at all switches. Once routing is achieved within the structured network, transfer to a destination termination device occurs through a single look-up table only when departing the network if multiple termination devices are present at that exit node. The routing operation between termination devices can therefore be achieved using a single mapping operation (if more than one termination device must be selected) and is backward compatible with devices external to the network and protocols used by those devices.

Abstract: Architectures, systems, and methods are provided for securing and prioritizing packets of data sent through a communication network. Each packet is assigned a security code and priority code as it enters the network. The security code or priority code may remain the same or change as it travels from node-to-node across the network. By assigning security and priority codes to each packet, maximum bandwidth allocation can be achieved among the nodes in a packet-switched environment. The assigned security and priority codes enter and travel through the network according to modules which have a hierarchical class or grouping. Thus, the security and priority information may be sent solely within one class or among classes depending on where, within the classes the data path exists.

Abstract: Architectures, systems, and methods are provided for securing and prioritizing packets of data sent through a communication network. Each packet is assigned a security code and priority code as it enters the network. The security code or priority code may remain the same or change as it travels from node-to-node across the network. By assigning security and priority codes to each packet, maximum bandwidth allocation can be achieved among the nodes in a packet-switched environment. The assigned security and priority codes enter and travel through the network according to modules which have a hierarchical class or grouping. Thus, the security and priority information may be sent solely within one class or among classes depending on where, within the classes the data path exists.

Abstract: An architecture, system and method are provided for efficiently transferring packets of data across a communication network. The communication network is structured such that there are hierarchical levels of high speed switches existing throughout the network. Distributed routing of packets is achieved by comparing identification numbers of only select switches with the destination address on a field-by-field basis. Not all fields need be compared at all switches. Once routing is achieved within the structured network, transfer to a destination termination device occurs through a single look-up table only when departing the network if multiple termination devices are present at that exit node. The routing operation between termination devices can therefore be achieved using a single mapping operation (if more than one termination device must be selected) and is backward compatible with devices external to the network and protocols used by those devices.

Abstract: An architecture, system and method are provided for transparently mapping addresses across multiple addressing domains and/or protocols. A destination of a packet can therefore be transferred from a first addressing domain within one network to a second addressing domain within another network, without inserting knowledge into the packet of the relationship between the two separate and independent domains. Transmission modules within one network can be identified with unique identification numbers or addresses assigned during configuration of those modules. The identification numbers assigned internal to the network can be mapped and placed upon the packet as the packet enters the network. Mapping, however, is minimal, knowing that relatively few external devices are connected to select internal devices and/or modules. The packet can then be mapped into the network, where it is then transferred across the network whereupon it is mapped to another network or termination device external to the network.

Abstract: An architecture, system and method are provided for transparently mapping addresses across multiple addressing domains and/or protocols. A destination of a packet can therefore be transferred from a first addressing domain within one network to a second addressing domain within another network, without inserting knowledge into the packet of the relationship between the two separate and independent domains. Transmission modules within one network can be identified with unique identification numbers or addresses assigned during configuration of those modules. The identification numbers assigned internal to the network can be mapped and placed upon the packet as the packet enters the network. Mapping, however, is minimal, knowing that relatively few external devices are connected to select internal devices and/or modules. The packet can then be mapped into the network, where it is then transferred across the network whereupon it is mapped to another network or termination device external to the network.

Abstract: A load/store unit comprising a load/store buffer and a memory access buffer. The load store buffer is coupled to a data cache and is configured to store information on memory operations. The memory access buffer is configured to store addresses and data associated with the requested addresses for at least one of the most recent memory operations. The memory access buffer, upon detecting a load memory operation, outputs data associated with the load memory operation's requested address. If the requested address is not stored within the memory access buffer, the memory access buffer is configured to store the load memory operation's requested address and associated data when it becomes available from the data cache. Similarly, store memory operation requested address and associated data is also stored.

Abstract: A microprocessor configured to rapidly decode variable-length instructions is disclosed. The microprocessor is configured with a predecoder and an instruction cache. The predecoder is configured to expand variable-length instructions to create fixed-length instructions by padding instruction fields within each variable-length instruction with constants until each field reaches a predetermined maximum width. The fixed-width instructions are then stored within the instruction cache and output for execution when a corresponding requested address is received. The instruction cache may store both variable- and fixed-width instructions, or just fixed-width instructions. An array of pointers may be used to access particular fixed-length instructions. The fixed-length instructions may be configured to all have the same fields and the same lengths, or they may be divided into groups, wherein instructions within each group have the same fields and the same lengths.

Abstract: An architecture, system and method are provided for transparently mapping addresses across multiple addressing domains and/or protocols. A destination of a packet can therefore be transferred from a first addressing domain within one network to a second addressing domain within another network, without inserting knowledge into the packet of the relationship between the two separate and independent domains. Transmission modules within one network can be identified with unique identification numbers or addresses assigned during configuration of those modules. The identification numbers assigned internal to the network can be mapped and placed upon the packet as the packet enters the network. Mapping, however, is minimal, knowing that relatively few external devices are connected to select internal devices and/or modules. The packet can then be mapped into the network, where it is then transferred across the network whereupon it is mapped to another network or termination device external to the network.

Abstract: A core snoop buffer apparatus is provide which stores addresses of pages from which instructions have been fetched but not yet retired (i.e. the instructions are outstanding within the instruction processing pipeline). Addresses corresponding to memory locations being modified are compared to the addresses stored in the core snoop buffer on a page basis. If a match is detected, then instructions are flushed from the instruction processing pipeline and refetched. In this manner, the instructions executed to the point of modifying registers or memory are correct in self-modifying code or multiprocessor environments. Instructions may be speculatively fetched and executed while retaining coherency with respect to changes to memory. The number of pages from which instructions are concurrently outstanding within the microprocessor are typically small compared to the number of cache lines outstanding or the number of instructions outstanding.