Abstract: A semiconductor device includes a first transistor and a first gate electrically coupled to the first transistor. A second transistor is positioned on top of the first transistor. A second gate is electrically coupled to the second transistor. A dielectric isolation layer is positioned between the first gate and the second gate. A first conductive contact is electrically coupled to the first gate. A second conductive contact is electrically coupled to the second gate. A control of the first gate through the first conductive contact is independent of a control of the second gate through the second conductive contact.

Abstract: A first semiconductor device includes an interfacial layer over a substrate, a first high-? dielectric layer over the interfacial layer, a second high-? dielectric layer over the first high-? dielectric layer, a Ti—Si mixing layer over the second high-? dielectric layer, and a gate electrode layer over the Ti—Si mixing layer. A second semiconductor device includes an interfacial layer over a substrate, a first high-? dielectric layer over the interfacial layer, a Ti—Si mixing layer over the first high-? dielectric layer, a second high-? dielectric layer over the Ti—Si mixing layer, and a gate electrode layer over the second high-? dielectric layer. The method includes forming an interfacial layer over a substrate, forming a first high-? dielectric layer over the interfacial layer, forming a second high-? dielectric layer over the first high-? dielectric layer, and forming a gate electrode layer over the second high-? dielectric layer.

Abstract: Embodiments of the present invention are directed to monolithic stacked field effect transistor (SFET) processing methods and resulting structures having dual middle dielectric isolation (MDI) separation. In a non-limiting embodiment of the invention, a first nanosheet is formed and a second nanosheet is vertically stacked over the first nanosheet. A gate is formed around a channel region of the first nanosheet and a channel region of the second nanosheet and a middle dielectric isolation structure is formed between the first nanosheet and the second nanosheet. The middle dielectric isolation structure includes a first middle dielectric isolation layer and a second middle dielectric isolation layer vertically stacked over the first middle dielectric isolation layer. A portion of the gate extends between the first middle dielectric isolation layer and the second middle dielectric isolation layer in the middle dielectric isolation structure.

Abstract: A semiconductor device includes a substrate having a first region and a second region separated from the first region by distance to define a space therebetween. A first semiconductor device including a gate dielectric is on the first region. The first semiconductor device can implement a FinFet-based input/output (I/O) device in the first region. A second semiconductor device excluding a gate dielectric is on the second region. The second semiconductor device can implement a nanosheet-based logic device in the second region.

Abstract: A semiconductor device includes a substrate; a set of first transistors positioned on an upper surface of the substrate, each of the set of first transistors comprising a first gate and a first dielectric; an insulating layer positioned on an upper surface of the set of first transistors; and a set of second transistors positioned over the set of first transistors and with the set of first transistors on an upper surface of the insulating layer, each of the set of second transistors having a second gate and a second dielectric; wherein each of the first dielectrics is connected to a sidewall of each of a corresponding first gate; and wherein each of the second dielectrics is connected to the insulating layer.

Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate, and a pFET transistor formed on the semiconductor substrate. The pFET transistor includes a plurality of channel regions. An uppermost channel region of the plurality of channel regions includes an uppermost active semiconductor layer and a capping layer formed on the uppermost active semiconductor layer.

Abstract: Embodiments of the present invention are directed to processing methods and resulting structures for non-shared metal gate integrations for transistors. In a non-limiting embodiment of the invention, a first nanosheet stack is formed in a first region of a substrate and a second nanosheet stack is formed in a second region of the substrate. A first work function metal stack is formed around nanosheets in the first nanosheet stack and nanosheets in the second nanosheet stack, and a first sacrificial material is formed around the first work function metal stack. The first sacrificial material in the second nanosheet stack is replaced with a second sacrificial material and the first sacrificial material and the first work function metal stack in the first nanosheet stack are replaced with a second work function metal stack. The second sacrificial material in the second nanosheet stack is replaced with a third work function metal stack.

Abstract: Semiconductor devices, integrated chips, and methods of forming the same include forming a fill over a stack of semiconductor layers. The stack of semiconductor layers includes a first sacrificial layer and a set of alternating second sacrificial layers and channel layers. A dielectric fin is formed over the stack of semiconductor layers. The first sacrificial layer and the second sacrificial layers are etched away, leaving the channel layers supported by the dielectric fin over an exposed substrate surface. A dielectric layer is conformally deposited on the exposed substrate surface, the dielectric layer having a consistent thickness across the top surface. A conductive material is deposited over the dielectric layer.

Abstract: Techniques are provided to fabricate semiconductor devices having a nanosheet field-effect transistor device disposed on a semiconductor substrate. The nanosheet field-effect transistor device includes a nanosheet stack structure including a semiconductor channel layer and a source/drain region in contact with an end portion of the semiconductor channel layer of the nanosheet stack structure. A trench formed in the source/drain region is filled with a metal-based material. The metal-based material filling the trench in the source/drain region mitigates the effect of source/drain material overfill on the contact resistance of the semiconductor device.

Abstract: A method includes forming a first nanosheet fin extending vertically from a first region of a substrate corresponding to a logic device and forming a second nanosheet fin extending vertically from a second region of the substrate corresponding to an input/output device. The first nanosheet fin includes first semiconductor channel layers vertically stacked over the first region. The second nanosheet fin includes an alternating sequence of semiconductor sacrificial layers and second semiconductor channel layers vertically stacked over the second region. An encapsulation layer is epitaxially grown along sidewalls of the alternating sequence of semiconductor sacrificial layers and second semiconductor channel layers, and an oxide layer is formed in contact with a top surface of an uppermost second semiconductor channel layer of the alternating sequence of semiconductor sacrificial layers and second semiconductor channel layers and in contact with opposite sidewalls of the encapsulation layer.

Abstract: A semiconductor structure is presented including a first field effect transistor (FET), the first FET including at least a first set of fins and a second set of fins, the first set of fins surrounded by a first work function metal (WFM) and the second set of fins surrounded by a second WFM and a second FET formed directly over the first FET, the second FET including at least a first nanosheet stack and a second nanosheet stack, the first nanosheet stack surrounded by a third WFM and the second nanosheet stack surrounded by a third WFM with dipoles. The semiconductor structure further includes first contacts disposed from the first and second WFMs of the first FET to back-end-of-line (BEOL) components and second contacts disposed from a backside power delivery network (BSPDN) through the third WFM of the second FET to a top surface of the first and second WFMs of the first FET.

Abstract: An integrated circuit structure includes a first combsheet field effect transistor (FET), which includes: a semiconductor substrate; a first plurality of semiconductor nanosheets that extend along a <101> crystallographic direction and that have horizontal surfaces oriented in (100) crystallographic planes and vertical sidewalls oriented in (110) crystallographic planes; and a semiconductor fin that is integrally attached to the nanosheets, extends along the nanosheets, and has horizontal sidewalls oriented in (100) crystallographic planes and vertical surfaces oriented in (110) crystallographic planes.

Abstract: A semiconductor structure includes a semiconductor substrate, with first, second, and third field effect transistors (FETs) formed on the substrate. A gate of the first FET includes a gate electrode, a first work function metal (WFM) layered with a first interfacial layer (IL) and a first high-k dielectric (HK); a gate of the second FET includes the first WFM layered with a second IL, a second HK, and a first dipole material; and a gate of the third FET includes the first WFM layered with a third IL, a third HK, the first dipole material, and a second dipole material. The first FET does not include the first dipole material and does not include the second dipole material, and the second FET does not include the second dipole material.

Abstract: A semiconductor structure includes a first nanosheet fin extending vertically from a first region of a substrate corresponding to a logic device and a second nanosheet fin extending vertically from a second region of the substrate corresponding to an input/output device. The first nanosheet fin includes first semiconductor channel layers vertically stacked over the first region of the substrate, while the second nanosheet fin includes an alternating sequence of semiconductor sacrificial layers and second semiconductor channel layers. The semiconductor structure further includes an epitaxially grown encapsulation layer disposed only along sidewalls of the second nanosheet fin.

Abstract: Embodiments of present invention provide a method of forming a transistor structure. The method includes receiving a first and a second gate region of a first and a second transistor, the second transistor being adjacent to the first transistor; forming a first work-function metal surrounding the first gate region; truncating the first work-function metal at a first boundary between the first transistor and the second transistor; forming one or more work-function metals surrounding the first gate region; truncating the one or more work-function metals at a second boundary between the first boundary and the second transistor; and forming another work-function metal surround the first and second gate regions. A transistor structure formed thereby is also provided.

Abstract: A semiconductor device includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer of the semiconductor device includes a standard-gate field-effect transistor. The second semiconductor layer of the semiconductor device includes an extended-gate field-effect transistor. The first semiconductor layer and the second semiconductor layer are formed on top of one another.

Abstract: A device is provided. The device includes an interfacial layer on a semiconductor device channel. The device further includes a dipole layer on the interfacial layer, and a gate dielectric layer on the dipole layer. The device further includes a first work function layer associated with a first field effect transistor device; and a second work function layer associated with a second field effect transistor device, such that the first field effect transistor device and second field effect transistor device each have a different threshold voltage than a first field effect transistor device and second field effect transistor device without a dipole layer.

Abstract: A semiconductor device is provided. The semiconductor device includes a bottom source/drain; a top source/drain; a fin provided between the bottom source/drain and the top source/drain, the fin including a first fin structure and a second fin structure that are symmetric to each other in a plan view. Each of the first and second fin structures includes a main fin extending laterally in a first direction, and first and second extension fins extending laterally from the main fin in a second direction perpendicular to the first direction. The main fin extends laterally in the first direction beyond where the first and second extension fins connect to the main fin.

Abstract: A semiconductor structure includes a semiconductor substrate, with first, second, and third field effect transistors (FETs) formed on the substrate. A gate of the first FET includes a gate electrode, a first work function metal (WFM) layered with a first interfacial layer (IL) and a first high-k dielectric (HK); a gate of the second FET includes the first WFM layered with a second IL, a second HK, and a first dipole material; and a gate of the third FET includes the first WFM layered with a third IL, a third HK, the first dipole material, and a second dipole material. The first FET does not include the first dipole material and does not include the second dipole material, and the second FET does not include the second dipole material.

Abstract: A semiconductor device including a first nanosheet device located on a substrate. The first nanosheet device includes a first plurality of nanosheets and each of the first plurality of nanosheets are surround by a first dipole. The first dipole has a first concentration of a first dipole material. A second nanosheet device located on the substrate. The second nanosheet device includes a second plurality of nanosheets and each of the second plurality of nanosheets are surround by a second dipole. The second dipole has a second concentration of a second dipole material. The first concentration and the second concentration are different.