Patents by Inventor Russell C. Zahorik
Russell C. Zahorik has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8264061Abstract: A device with a memory array is disclosed. In one embodiment, the memory array includes a plurality of memory cells, each including an electrode and a phase change material. The electrode may be disposed on a substrate, the electrode having a sublithographic lateral dimension parallel to the substrate. The phase change material may be coupled to the electrode and include a lateral dimension parallel to the substrate and greater than the sublithographic lateral dimension of the electrode.Type: GrantFiled: November 2, 2010Date of Patent: September 11, 2012Assignee: Round Rock Research, LLCInventor: Russell C. Zahorik
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Patent number: 8053371Abstract: A process and apparatus for locally removing any material, such as a refractory metal, in particular tungsten, from any desired area of a wafer, such as an alignment mark area of a silicon wafer in process during the formation of integrated circuits thereon.Type: GrantFiled: February 26, 2007Date of Patent: November 8, 2011Assignee: Micron Technology, Inc.Inventors: Russell C. Zahorik, Guy F. Hudson, Hugh E. Stroupe, Todd A. Dobson, Brian F. Gordon
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Publication number: 20110042640Abstract: A device with a memory array is disclosed. In one embodiment, the memory array includes a plurality of memory cells, each including an electrode and a phase change material. The electrode may be disposed on a substrate, the electrode having a sublithographic lateral dimension parallel to the substrate. The phase change material may be coupled to the electrode and include a lateral dimension parallel to the substrate and greater than the sublithographic lateral dimension of the electrode.Type: ApplicationFiled: November 2, 2010Publication date: February 24, 2011Applicant: ROUND ROCK RESEARCH, LLCInventor: Russell C. Zahorik
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Patent number: 7838416Abstract: A semiconductor device is disclosed. In one embodiment, the semiconductor device includes a memory cell, which in turn includes an electrode and a phase change material. The electrode may be disposed on a substrate and include a sublithographic lateral dimension parallel to the substrate. The phase change material may be coupled to the electrode and include a lateral dimension parallel to the substrate and greater than the sublithographic lateral dimension of the electrode. Various semiconductor devices and manufacturing methods are also provided.Type: GrantFiled: February 24, 2010Date of Patent: November 23, 2010Assignee: Round Rock Research, LLCInventor: Russell C. Zahorik
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Publication number: 20100151665Abstract: A semiconductor device is disclosed. In one embodiment, the semiconductor device includes a memory cell, which in turn includes an electrode and a phase change material. The electrode may be disposed on a substrate and include a sublithographic lateral dimension parallel to the substrate. The phase change material may be coupled to the electrode and include a lateral dimension parallel to the substrate and greater than the sublithographic lateral dimension of the electrode. Various semiconductor devices and manufacturing methods are also provided.Type: ApplicationFiled: February 24, 2010Publication date: June 17, 2010Applicant: MICRON TECHNOLOGY, INCInventor: Russell C. Zahorik
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Patent number: 7687881Abstract: A semiconductor device is disclosed. In one embodiment, the semiconductor device includes a memory cell, which in turn includes an electrode and a phase change material. The electrode may be disposed on a substrate and include a sublithographic lateral dimension parallel to the substrate. The phase change material may be coupled to the electrode and include a lateral dimension parallel to the substrate and greater than the sublithographic lateral dimension of the electrode. Various semiconductor devices and manufacturing methods are also provided.Type: GrantFiled: January 21, 2009Date of Patent: March 30, 2010Assignee: Micron Technology, Inc.Inventor: Russell C. Zahorik
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Publication number: 20090121212Abstract: A semiconductor device is disclosed. In one embodiment, the semiconductor device includes a memory cell, which in turn includes an electrode and a phase change material. The electrode may be disposed on a substrate and include a sublithographic lateral dimension parallel to the substrate. The phase change material may be coupled to the electrode and include a lateral dimension parallel to the substrate and greater than the sublithographic lateral dimension of the electrode. Various semiconductor devices and manufacturing methods are also provided.Type: ApplicationFiled: January 21, 2009Publication date: May 14, 2009Applicant: Micron Technology, Inc.Inventor: Russell C. Zahorik
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Patent number: 7494922Abstract: A method of manufacturing a memory cell is disclosed. In one embodiment, the method includes forming an electrode including an outer surface that is substantially circular and an exposed surface that has a sublithographic dimension in a direction parallel to the exposed surface. Further, the method may also include forming a layer of phase change material coupled to the exposed surface of the electrode. Various semiconductor devices and additional methods of manufacturing memory cells are also provided.Type: GrantFiled: September 25, 2007Date of Patent: February 24, 2009Assignee: Micron Technology, Inc.Inventor: Russell C. Zahorik
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Patent number: 7453082Abstract: A memory cell and a method of fabricating the memory cell having a small active area are provided. By forming a spacer in a window that is sized at the photolithographic limit, in one embodiment, a pore may be formed in dielectric layer which is smaller than the photolithographic limit. Electrode material is deposited into the pore, and a layer of structure changing material, such as chalcogenide, is deposited onto the lower electrode, thus creating a memory element having an extremely small and reproducible active area.Type: GrantFiled: July 27, 2006Date of Patent: November 18, 2008Assignee: Micron Technology, Inc.Inventors: Alan R. Reinberg, Renee Zahorik, legal representative, Russell C. Zahorik
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Patent number: 7273809Abstract: A method for fabricating an ultra-small electrode or plug contact for use in chalcogenide memory cells specifically, and in semiconductor devices generally, in which disposable spacers are utilized to fabricate ultra-small pores into which the electrodes are formed. The electrodes thus defined have minimum lateral dimensions ranging from approximately 500 to 4000 Angstroms. The pores thus defined may then be used to fabricate a chalcogenide memory cell or other semiconductor devices.Type: GrantFiled: August 31, 2004Date of Patent: September 25, 2007Assignee: Micron Technology, Inc.Inventor: Russell C. Zahorik
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Patent number: 7244681Abstract: A process and apparatus for locally removing any material, such as a refractory metal, in particular tungsten, from any desired area of a wafer, such as an alignment mark area of a silicon wafer in process during the formation of integrated circuits thereon.Type: GrantFiled: August 25, 2003Date of Patent: July 17, 2007Assignee: Micron Technology, Inc.Inventors: Renee Zahorik, legal representative, Guy F. Hudson, Hugh E. Stroupe, Todd A. Dobson, Brian F. Gordon, Russell C. Zahorik, deceased
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Patent number: 7102151Abstract: A memory cell and a method of fabricating the memory cell having a small active area. By forming a spacer in a window that is sized at the photolithographic limit, a pore may be formed in dielectric layer which is smaller than the photolithographic limit. Electrode material is deposited into the pore, and a layer of structure changing material, such as chalcogenide, is deposited onto the lower electrode, thus creating a memory element having an extremely small and reproducible active area.Type: GrantFiled: June 21, 2004Date of Patent: September 5, 2006Assignee: Micron Technology, Inc.Inventors: Alan R. Reinberg, Renee Zahorik, legal representative, Russell C. Zahorik, deceased
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Patent number: 6984874Abstract: A recess having a height-to-width aspect ratio from about 6:1 to about 10:1 in a semiconductor structure is disclosed with a method of forming the same. In a first embodiment, a refractory metal layer is formed in the recess, which can be a trench, a contact hole, or a combination thereof. A refractory metal nitride layer is then formed on the refractory metal layer. A heat treatment is used to form a metal silicide contact at the bottom of the contact hole upon a semiconductor material. In a first alternative method, an ammonia high-temperature treatment is conducted to remove undesirable impurities within the refractory metal nitride layer lining the contact hole and to replace the impurities with more nitrogen. In a second alternative method, a second refractory metal nitride layer is formed by PVD upon the first refractory metal nitride layer. In either alternative, a metallization layer is deposited within the recess.Type: GrantFiled: August 10, 2004Date of Patent: January 10, 2006Assignee: Micron Technology, Inc.Inventors: John H. Givens, Russell C. Zahorik, Brenda D. Kraus
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Patent number: 6889698Abstract: A process and apparatus for locally removing any material, such as a refractory metal, in particular tungsten, from any desired area of a wafer, such as an alignment mark area of a silicon wafer in process during the formation of integrated circuits thereon.Type: GrantFiled: February 14, 2003Date of Patent: May 10, 2005Assignee: Micron Technology, Inc.Inventors: Russell C. Zahorik, Guy F. Hudson, Hugh E. Stroupe, Todd A. Dobson, Brian F. Gordon
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Patent number: 6812139Abstract: A recess having a height-to-width aspect ratio from about 6:1 to about 10:1 in a semiconductor structure is taught with a method of forming the same. In a first embodiment, a refractory metal layer is formed in the recess, which can be a trench, a contact hole, or a combination thereof. A refractory metal nitride layer is then formed on the refractory metal layer. A heat treatment is used to form a metal silicide contact at the bottom of the contact hole upon a semiconductor material. In a first alternative method, an ammonia high-temperature treatment is conducted to remove undesirable impurities within the refractory metal nitride layer lining the contact hole and to replace the impurities with more nitrogen. In a second alternative method, a second refractory metal nitride layer is formed by PVD upon the first refractory metal nitride layer. In either alternative, a metallization layer is deposited within the recess.Type: GrantFiled: October 25, 2002Date of Patent: November 2, 2004Assignee: Micron Technology, Inc.Inventors: John H. Givens, Russell C. Zahorik, Brenda D. Kraus
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Patent number: 6797612Abstract: A method for fabricating an ultra-small electrode or plug contact for use in chalcogenide memory cells specifically, and in semiconductor devices generally, in which disposable spacers are utilized to fabricate ultra-small pores into which the electrodes are formed. The electrodes thus defined have minimum lateral dimensions ranging from approximately 500 to 4000 Angstroms. The pores thus defined may then be used to fabricate a chalcogenide memory cell or other semiconductor devices.Type: GrantFiled: March 7, 2003Date of Patent: September 28, 2004Assignee: Micron Technology, Inc.Inventor: Russell C. Zahorik
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Patent number: 6777705Abstract: A memory cell and a method of fabricating the memory cell having a small active area. By forming a spacer in a window that is sized at the photolithographic limit, a pore may be formed in dielectric layer which is smaller than the photolithographic limit. Electrode material is deposited into the pore, and a layer of structure changing material, such as chalcogenide, is deposited onto the lower electrode, thus creating a memory element having an extremely small and reproducible active area.Type: GrantFiled: December 19, 2000Date of Patent: August 17, 2004Assignee: Micron Technology, Inc.Inventors: Alan R. Reinberg, Russell C. Zahorik
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Publication number: 20040038543Abstract: A process and apparatus for locally removing any material, such as a refractory metal, in particular tungsten, from any desired area of a wafer, such as an alignment mark area of a silicon wafer in process during the formation of integrated circuits thereon.Type: ApplicationFiled: August 25, 2003Publication date: February 26, 2004Inventors: Russell C. Zahorik, Guy F. Hudson, Hugh E. Stroupe, Todd A. Dobson, Brian F. Gordon, Renee Zahorik
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Patent number: 6690077Abstract: Titanium aluminum nitrogen (“Ti—Al—N”) is deposited onto a semiconductor substrate area to serve as an antireflective coating. For wiring line fabrication processes, the Ti—Al—N layer serves as a cap layer which prevents unwanted reflection of photolithography light (i.e., photons) during fabrication. For field emission display devices (FEDs), the Ti—Al—N layer prevents light originating at the display screen anode from penetrating transistor junctions that would hinder device operation. For the wiring line embodiment an aluminum conductive layer and a titanium-aluminum underlayer are formed beneath the antireflective cap layer. The Ti—Al underlayer reduces the shrinkage which occurs in the aluminum conductive layer during heat treatment.Type: GrantFiled: March 17, 2000Date of Patent: February 10, 2004Assignee: Micron Technology, Inc.Inventors: Everett A. McTeer, Russell C. Zahorik, Scott G. Meikle
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Patent number: RE39413Abstract: The present invention is a semiconductor wafer that enhances polish-stop endpointing in chemical-mechanical planarization processes. The semiconductor wafer has a substrate with a device feature formed on the substrate, a stratum of low friction material positioned over the substrate, and an upper layer deposited on the low friction material stratum. The low friction stratum has a polish-stop surface positioned at a level substantially proximate to a desired endpoint of the chemical-mechanical planarization process. The upper layer, which is made from either a conductive material or an insulative material, has a higher polishing rate than that of the low friction stratum. In operation, the low friction stratum resists chemical-mechanical planarization with either hard or soft polishing pads to stop the planarization process at the desired endpoint.Type: GrantFiled: May 2, 2002Date of Patent: November 28, 2006Assignee: Micron Technology, Inc.Inventors: Guy F. Hudson, Renee Zahorik, Russell C. Zahorik