Abstract: Managing delivery of power to one or more hardware memory devices in a computer system. The computer system is configured with a processor and at least two hardware memory devices. A temperature monitor tool is employed to monitor the hardware memory devices. Management of an addressable subset of the hardware memory devices is employed in response to the monitored temperature reading.

Abstract: Managing delivery of power to one or more hardware memory devices in a computer system. The computer system is configured with a processor and at least two hardware memory devices. A temperature monitor tool is employed to monitor the hardware memory devices. Management of an addressable subset of the hardware memory devices is employed in response to the monitored temperature reading.

Abstract: A system, method and computer program product for optimizing a software system through scenario evaluation. In accordance with the disclosed technique, a request is received for evaluation of an operational scenario that operates over an environment that is a superset of existing system capabilities encompassing system features or parameters that are not available in the currently running system. A knowledge base is consulted to derive recommendations with respect to operating parameters that may be collected to evaluate the scenario, mechanisms for gathering data relating to the parameters, and data evaluator operations for deriving a data evaluation result based on the data gathering. The knowledge base is further consulted to determine a reconfiguration recommendation based on the result. Scenario evaluation is performed based on simulation of the reconfiguration recommendation using the data evaluation result to determine efficacy of the scenario.

Abstract: Managing delivery of power to one or more hardware memory devices in a computer system. The computer system is configured with a processor and at least two hardware memory devices. An energy exchange threshold for the computer system is set, and management of one or more of the hardware memory devices is employed when the computer system exceeds an energy exchange threshold.

Abstract: Facilitating error handling of computing environments, including those environments having file systems. Responsive to an entity of the computing environment, such as a client of a file system, obtaining at least an indication of an error, a portion of functionality of the entity is automatically frozen. The obtaining is, for instance, responsive to an event of another entity of the computing environment, such as a server of the file system. Eventually, the frozen functionality is thawed allowing the functionality to proceed.

Abstract: Apparatus and Method for Selective Power Reduction of Memory Hardware A method and apparatus are provided for managing delivery of power to one or more hardware memory devices in a computer system. The computer system is configured with a processor and at least two hardware memory devices. An energy exchange threshold for the computer system is set, and management of one or more of the hardware memory devices is employed when the computer system exceeds an energy exchange threshold.

Abstract: A system, method and computer program product for optimizing a software system through scenario evaluation. In accordance with the disclosed technique, a request is received for evaluation of an operational scenario that operates over an environment that is a superset of existing system capabilities encompassing system features or parameters that are not available in the currently running system. A knowledge base is consulted to derive recommendations with respect to operating parameters that may be collected to evaluate the scenario, mechanisms for gathering data relating to the parameters, and data evaluator operations for deriving a data evaluation result based on the data gathering. The knowledge base is further consulted to determine a reconfiguration recommendation based on the result. Scenario evaluation is performed based on simulation of the reconfiguration recommendation using the data evaluation result to determine efficacy of the scenario.

Abstract: Facilitating error handling of computing environments, including those environments having file systems. Responsive to an entity of the computing environment, such as a client of a file system, obtaining at least an indication of an error, a portion of functionality of the entity is automatically frozen. The obtaining is, for instance, responsive to an event of another entity of the computing environment, such as a server of the file system. Eventually, the frozen functionality is thawed allowing the functionality to proceed.

Abstract: Facilitating error handling of computing environments, including those environments having file systems. Responsive to an entity of the computing environment, such as a client of a file system, obtaining at least an indication of an error, a portion of functionality of the entity is automatically frozen. The obtaining is, for instance, responsive to an event of another entity of the computing environment, such as a server of the file system. Eventually, the frozen functionality is thawed allowing the functionality to proceed.

Abstract: Facilitating error handling of computing environments, including those environments having file systems. Responsive to an entity of the computing environment, such as a client of a file system, obtaining at least an indication of an error, a portion of functionality of the entity is automatically frozen. The obtaining is, for instance, responsive to an event of another entity of the computing environment, such as a server of the file system. Eventually, the frozen functionality is thawed allowing the functionality to proceed.

Abstract: A cache coherency test exercises cache coherency logic exhaustively such that any cache coherency failures liable to occur will occur. The CPU(s) which caused the failure is automatically identified by performing an automatic CPU sort. In particular, cache coherency is tested by causing each processor in the system to perform a sequence of read and write accesses to main memory and to its own cache memory so as to cause substantially every possible sequence of cache coherency bus operations. Each processor tests consistency of data read by it with data written by it. As long as no processor detects an error, read and write accesses are continued for a predetermined period of time. When any processor detects an error, each CPU is disabled, one at a time, to see if the remaining CPUs can run the test successfully. If they do not, then every combination of two CPUs are disabled, then every combination of three, etc. In this manner, a maximum running set of CPUs is identified.