Patents by Inventor Russell K. Mortensen
Russell K. Mortensen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11978730Abstract: An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.Type: GrantFiled: January 28, 2022Date of Patent: May 7, 2024Assignee: Intel CorporationInventors: Russell K. Mortensen, Robert M. Nickerson, Nicholas R. Watts
-
Publication number: 20240114622Abstract: An electronic device includes a substrate including a core layer; a cavity formed in the core layer, wherein the cavity includes sidewalls plated with a conductive material; a prefabricated passive electronic component disposed in the cavity; and a cavity sidewall connection providing electrical continuity from the plated cavity sidewalls to a first surface of the substrate and to a second surface of the substrate.Type: ApplicationFiled: September 29, 2022Publication date: April 4, 2024Inventors: Kristof Darmawikarta, Srinivas Venkata Ramanuja Pietambaram, Tarek A. Ibrahim, Cary Kuliasha, Siddharth K. Alur, Jung Kyu Han, Beomseok Choi, Russell K. Mortensen, Andrew Collins, Haobo Chen, Brandon C. Marin
-
Publication number: 20240006401Abstract: An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.Type: ApplicationFiled: September 14, 2023Publication date: January 4, 2024Applicant: Intel CorporationInventors: Russell K. MORTENSEN, Robert M. NICKERSON, Nicholas R. WATTS
-
Patent number: 11798932Abstract: An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.Type: GrantFiled: June 30, 2022Date of Patent: October 24, 2023Assignee: Intel CorporationInventors: Russell K. Mortensen, Robert M. Nickerson, Nicholas R. Watts
-
Publication number: 20220344318Abstract: An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.Type: ApplicationFiled: June 30, 2022Publication date: October 27, 2022Applicant: Intel CorporationInventors: Russell K. MORTENSEN, Robert M. Nickerson, Nicholas R. Watts
-
Publication number: 20220157799Abstract: An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.Type: ApplicationFiled: January 28, 2022Publication date: May 19, 2022Applicant: Intel CorporationInventors: Russell K. MORTENSEN, Robert M. NICKERSON, Nicholas R. WATTS
-
Publication number: 20210296241Abstract: Embodiments may relate to a microelectronic package that includes an active die at a first side of the substrate and an interconnect at a second side of the substrate. A high-speed input/output (HSIO) die may also be coupled with the first side of substrate. The HSIO die may be coupled with the active die by a bridge. Other embodiments may be described or claimed.Type: ApplicationFiled: March 20, 2020Publication date: September 23, 2021Applicant: Intel CorporationInventors: Arghya Sain, Lesley A. Polka Wood, Russell K. Mortensen
-
Patent number: 10607976Abstract: An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.Type: GrantFiled: March 31, 2016Date of Patent: March 31, 2020Assignee: Intel CorporationInventors: Russell K. Mortensen, Robert M. Nickerson, Nicholas R. Watts
-
Patent number: 10453799Abstract: Embodiments of the present disclosure are directed towards package assemblies, as well as methods for forming package assemblies and systems incorporating package assemblies. A package assembly may include a substrate including a plurality of build-up layers, such as bumpless build-up layer (BBUL). In various embodiments, electrical routing features may be disposed on an outer surface of the substrate. In various embodiments, a primary logic die and a second die or capacitor may be embedded in the plurality of build-up layers. In various embodiments, an electrical path may be defined in the plurality of build-up layers to route electrical power or a ground signal between the second die or capacitor and the electrical routing features, bypassing the primary logic die.Type: GrantFiled: November 8, 2016Date of Patent: October 22, 2019Assignee: INTEL CORPORATIONInventors: Deepak V. Kulkarni, Russell K. Mortensen, John S. Guzek
-
Patent number: 10446530Abstract: An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.Type: GrantFiled: August 16, 2011Date of Patent: October 15, 2019Assignee: Intel CorporationInventors: Russell K. Mortensen, Robert M. Nickerson, Nicholas R. Watts
-
Publication number: 20170125351Abstract: Embodiments of the present disclosure are directed towards package assemblies, as well as methods for forming package assemblies and systems incorporating package assemblies. A package assembly may include a substrate including a plurality of build-up layers, such as bumpless build-up layer (BBUL). In various embodiments, electrical routing features may be disposed on an outer surface of the substrate. In various embodiments, a primary logic die and a second die or capacitor may be embedded in the plurality of build-up layers. In various embodiments, an electrical path may be defined in the plurality of build-up layers to route electrical power or a ground signal between the second die or capacitor and the electrical routing features, bypassing the primary logic die.Type: ApplicationFiled: November 8, 2016Publication date: May 4, 2017Inventors: Deepak V. Kulkarni, Russell K. Mortensen, John S. Guzek
-
Patent number: 9496211Abstract: Embodiments of the present disclosure are directed towards package assemblies, as well as methods for forming package assemblies and systems incorporating package assemblies. A package assembly may include a substrate including a plurality of build-up layers, such as bumpless build-up layer (BBUL). In various embodiments, electrical routing features may be disposed on an outer surface of the substrate. In various embodiments, a primary logic die and a second die or capacitor may be embedded in the plurality of build-up layers. In various embodiments, an electrical path may be defined in the plurality of build-up layers to route electrical power or a ground signal between the second die or capacitor and the electrical routing features, bypassing the primary logic die.Type: GrantFiled: November 21, 2012Date of Patent: November 15, 2016Assignee: INTEL CORPORATIONInventors: Deepak V. Kulkarni, Russell K. Mortensen, John S. Guzek
-
Publication number: 20160218093Abstract: An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.Type: ApplicationFiled: March 31, 2016Publication date: July 28, 2016Applicant: Intel CorporationInventors: Russell K. Mortensen, Robert M. Nickerson, Nicholas R. Watts
-
Publication number: 20160133557Abstract: An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.Type: ApplicationFiled: December 24, 2015Publication date: May 12, 2016Applicant: Intel CorporationInventors: Russell K. Mortensen, Robert M. Nickerson, Nicholas R. Watts
-
Publication number: 20140138845Abstract: Embodiments of the present disclosure are directed towards package assemblies, as well as methods for forming package assemblies and systems incorporating package assemblies. A package assembly may include a substrate comprising a plurality of build-up layers, such as BBUL. In various embodiments, electrical routing features may be disposed on an outer surface of the substrate. In various embodiments, a primary logic die and a second die or capacitor may be embedded in the plurality of build-up layers. In various embodiments, an electrical path may be defined in the plurality of build-up layers to route electrical power or a ground signal between the second die or capacitor and the electrical routing features, bypassing the primary logic die.Type: ApplicationFiled: November 21, 2012Publication date: May 22, 2014Inventors: Deepak V. Kulkarni, Russell K. Mortensen, John S. Guzek
-
Publication number: 20130271907Abstract: An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.Type: ApplicationFiled: August 16, 2011Publication date: October 17, 2013Inventors: Russell K. Mortensen, Robert M. Nickerson, Nicholas R. Watts