Abstract: Multiphase voltage regulator systems are disclosed which include parallel signal pathways that functionally cooperate to provide an analog output signal at a constant, or substantially constant, voltage. The parallel signal pathways generate energy storage element charging signals to charge and/or discharge energy storage elements. Energy provided by discharging energy storage elements is thereafter combined to provide the analog output signal. Moreover, the parallel signal pathways compare one of the energy storage element charging signals with a reference input signal to provide a global error correction signal representing a difference, or error, between the reference input signal and the analog output signal. The parallel signal pathways thereafter adjust the energy storage element charging signals in accordance with the global error correction signal to lessen this difference or error.

Abstract: Multiphase voltage regulator systems are disclosed which include parallel signal pathways that functionally cooperate to provide an analog output signal at a constant, or substantially constant, voltage. The parallel signal pathways generate energy storage element charging signals to charge and/or discharge energy storage elements. Energy provided by discharging energy storage elements is thereafter combined to provide the analog output signal. Moreover, the parallel signal pathways compare one of the energy storage element charging signals with a reference input signal to provide a global error correction signal representing a difference, or error, between the reference input signal and the analog output signal. The parallel signal pathways thereafter adjust the energy storage element charging signals in accordance with the global error correction signal to lessen this difference or error.

Abstract: Multiphase voltage regulator systems are disclosed which include parallel signal pathways that functionally cooperate to provide an analog output signal at a constant, or substantially constant, voltage. The parallel signal pathways generate energy storage element charging signals to charge and/or discharge energy storage elements. Energy provided by discharging energy storage elements is thereafter combined to provide the analog output signal. Moreover, the parallel signal pathways compare one of the energy storage element charging signals with a reference input signal to provide a global error correction signal representing a difference, or error, between the reference input signal and the analog output signal. The parallel signal pathways thereafter adjust the energy storage element charging signals in accordance with the global error correction signal to lessen this difference or error.

Abstract: Multiphase voltage regulator systems are disclosed which include parallel signal pathways that functionally cooperate to provide an analog output signal at a constant, or substantially constant, voltage. The parallel signal pathways generate energy storage element charging signals to charge and/or discharge energy storage elements. Energy provided by discharging energy storage elements is thereafter combined to provide the analog output signal. Moreover, the parallel signal pathways compare one of the energy storage element charging signals with a reference input signal to provide a global error correction signal representing a difference, or error, between the reference input signal and the analog output signal. The parallel signal pathways thereafter adjust the energy storage element charging signals in accordance with the global error correction signal to lessen this difference or error.

Abstract: A pneumatic system utilizes a pneumatic cylinder to deploy and retract a bimini top. The pneumatic system also provides pressurized air to additional peripheral devices. A bimini top assembly includes links to deploy and retract a bimini top with an actuator.

Abstract: Multiphase voltage regulator systems are disclosed which include parallel signal pathways that functionally cooperate to provide an analog output signal at a constant, or substantially constant, voltage. The parallel signal pathways generate energy storage element charging signals to charge and/or discharge energy storage elements. Energy provided by discharging energy storage elements is thereafter combined to provide the analog output signal. Moreover, the parallel signal pathways compare one of the energy storage element charging signals with a reference input signal to provide a global error correction signal representing a difference, or error, between the reference input signal and the analog output signal. The parallel signal pathways thereafter adjust the energy storage element charging signals in accordance with the global error correction signal to lessen this difference or error.

Abstract: Multiphase voltage regulator systems are disclosed which include parallel signal pathways that functionally cooperate to provide an analog output signal at a constant, or substantially constant, voltage. The parallel signal pathways generate energy storage element charging signals to charge and/or discharge energy storage elements. Energy provided by discharging energy storage elements is thereafter combined to provide the analog output signal. Moreover, the parallel signal pathways compare one of the energy storage element charging signals with a reference input signal to provide a global error correction signal representing a difference, or error, between the reference input signal and the analog output signal. The parallel signal pathways thereafter adjust the energy storage element charging signals in accordance with the global error correction signal to lessen this difference or error.

Abstract: Multiphase voltage regulator systems are disclosed which include parallel signal pathways that functionally cooperate to provide an analog output signal at a constant, or substantially constant, voltage. The parallel signal pathways generate energy storage element charging signals to charge and/or discharge energy storage elements. Energy provided by discharging energy storage elements is thereafter combined to provide the analog output signal. Moreover, the parallel signal pathways compare one of the energy storage element charging signals with a reference input signal to provide a global error correction signal representing a difference, or error, between the reference input signal and the analog output signal. The parallel signal pathways thereafter adjust the energy storage element charging signals in accordance with the global error correction signal to lessen this difference or error.

Abstract: A circuit includes a first switch, a second switch, a first delay circuit and a second delay circuit. The first switch includes a first terminal, and the second switch includes a second terminal. The first circuit is coupled to the first terminal and the second terminal. The first circuit is configured to alternately turn ON the first switch and the second switch in accordance with an input signal and a delay setting. The delay setting corresponds to a delay between successive ON times of the first switch and the second switch. The second circuit is coupled to the first circuit. The second circuit is configured to monitor a first voltage on the first terminal and a second voltage on the second terminal, and to generate the delay setting based on at least the first voltage on the first terminal, or the second voltage on the second terminal.

Abstract: A regulator circuit comprises: a regulator output node; at least (N+1) regulator control circuits, N being an integer greater than 1; N drivers, each one of the N drivers including: a multiplexer having an input port and an output port, the input port of the multiplexer being coupled with output nodes of the at least (N+1) regulator control circuits; an adjuster circuit configured to adjust a level of a current supplied by the driver to the regulator output node; and a task controller. The task controller is configured to: set a first one of the N+1 regulator control circuits to be idle during a first cycle of a clock signal; and set a second one of the N+1 regulator control circuits to be idle during a second cycle of the clock signal.

Abstract: A multi-phase buck converter comprises a first comparator, a second comparator and a counter. The first comparator has a first node connected to a first voltage reference and a second node. The second comparator has a first node connected to a second voltage reference and a second node. The second node of the second comparator and the second node of the first comparator are together connected to an input voltage from an active phase of the buck converter. The counter is configured to adjust a number of active phases of the buck converter based on the input voltage.

Abstract: A multi-phase buck converter comprises a first comparator, a second comparator and a counter. The first comparator has a first node connected to a first voltage reference and a second node. The second comparator has a first node connected to a second voltage reference and a second node. The second node of the second comparator and the second node of the first comparator are together connected to an input voltage from an active phase of the buck converter. The counter is configured to adjust a number of active phases of the buck converter based on the input voltage.

Abstract: A circuit includes a first switch, a second switch, a first delay circuit and a second delay circuit. The first switch includes a first terminal, and the second switch includes a second terminal. The first circuit is coupled to the first terminal and the second terminal. The first circuit is configured to alternately turn ON the first switch and the second switch in accordance with an input signal and a delay setting. The delay setting corresponds to a delay between successive ON times of the first switch and the second switch. The second circuit is coupled to the first circuit. The second circuit is configured to monitor a first voltage on the first terminal and a second voltage on the second terminal, and to generate the delay setting based on at least the first voltage on the first terminal, or the second voltage on the second terminal.

Abstract: A regulator circuit comprises: a regulator output node; at least (N+1) regulator control circuits, N being an integer greater than 1; N drivers, each one of the N drivers including: a multiplexer having an input port and an output port, the input port of the multiplexer being coupled with output nodes of the at least (N+1) regulator control circuits; an adjuster circuit configured to adjust a level of a current supplied by the driver to the regulator output node; and a task controller. The task controller is configured to: set a first one of the N+1 regulator control circuits to be idle during a first cycle of a clock signal; and set a second one of the N+1 regulator control circuits to be idle during a second cycle of the clock signal.

Abstract: A circuit includes a first switch, a second switch, a first delay circuit and a second delay circuit. The first switch includes a first terminal, and the second switch includes a second terminal. The first delay circuit is coupled to the first terminal and the second terminal. The first delay circuit is configured to alternately turn ON the first switch and the second switch in accordance with an input signal and with a delay between successive ON times of the first switch and the second switch. The second delay circuit is coupled to the first terminal and the second terminal. The second delay circuit is configured to control the first delay circuit to generate the delay in accordance with a stored setting of the delay, a first voltage on the first terminal, or a second voltage on the second terminal.

Abstract: A regulator circuit includes a regulator output node, at least (N+1) regulator control circuits, and N drivers. N is an integer greater than 1. Each one of the N drivers includes a multiplexer, a driver stage, and a pre-driver stage. The multiplexer includes an input port and an output port, where the input port of the multiplexer is coupled with output nodes of the at least (N+1) regulator control circuits. The driver stage is coupled with the regulator output node. The pre-driver stage is configured to control the driver stage based on a signal on the output port of the multiplexer.

Abstract: A circuit includes a first switch, a second switch, a first delay circuit and a second delay circuit. The first switch includes a first terminal, and the second switch includes a second terminal. The first delay circuit is coupled to the first terminal and the second terminal. The first delay circuit is configured to alternately turn ON the first switch and the second switch in accordance with an input signal and with a delay between successive ON times of the first switch and the second switch. The second delay circuit is coupled to the first terminal and the second terminal. The second delay circuit is configured to control the first delay circuit to generate the delay in accordance with a stored setting of the delay, a first voltage on the first terminal, or a second voltage on the second terminal.

Abstract: A driving circuit includes first and second switches coupled in series, a delay generating circuit and a delay controlling circuit. The delay generating circuit and the delay controlling circuit are coupled to first and second control terminals of the first and second switches. The delay generating circuit is configured to alternately turn ON the first switch and the second switch in accordance with an input signal and with a delay between successive ON times of the first switch and the second switch. The delay controlling circuit is configured to store a setting of the delay, and control the delay generating circuit to generate the delay in accordance with the stored setting, a first voltage on the first control terminal and a second voltage on the second control terminal.

Abstract: A regulator circuit includes a regulator output node, at least (N+1) regulator control circuits, and N drivers. N is an integer greater than 1. Each one of the N drivers includes a multiplexer, a driver stage, and a pre-driver stage. The multiplexer includes an input port and an output port, where the input port of the multiplexer is coupled with output nodes of the at least (N+1) regulator control circuits. The driver stage is coupled with the regulator output node. The pre-driver stage is configured to control the driver stage based on a signal on the output port of the multiplexer.

Abstract: A driving circuit includes first and second switches coupled in series, a delay generating circuit and a delay controlling circuit. The delay generating circuit and the delay controlling circuit are coupled to first and second control terminals of the first and second switches. The delay generating circuit is configured to alternately turn ON the first switch and the second switch in accordance with an input signal and with a delay between successive ON times of the first switch and the second switch. The delay controlling circuit is configured to store a setting of the delay, and control the delay generating circuit to generate the delay in accordance with the stored setting, a first voltage on the first control terminal and a second voltage on the second control terminal.