Abstract: A system for deriving and managing RIA knowledge employs a data collection server and data processing system. The data collection server is configured to communicate with at least one data source to collect publically-available information pertaining to RIAs and stores such information in a first database. The data processing system processes the publically-available information stored in the first database to derive artifacts representing the publically-available information as well as additional artifacts that represent useful information beyond the publically-available information, and stores the artifacts and additional artifacts in a second database for output and/or analysis by users. The artifacts and additional artifacts that pertain to a particular RIA can be derived from both structured and unstructured data reported by the particular RIA to a regulatory authority.

Abstract: One or more technologies described herein can be used for viewing results of a simulation of a software executable in a multi-processor electronic circuit design. A debug environment can display simulation results related to the multiple processors, for example, as a correlated software debug view of the processors. In at least some embodiments, the disclosed technologies can be used to examine a correlation between an error in the simulation results and one or more inter-processor synchronization events.

Abstract: In some embodiments disclosed herein, the execution of a software program by processor can be simulated using two models of the processor: one “detailed” model that offers a relatively high level of detail and operates relatively slowly; and another “fast” model that offers a relatively low level of detail and operates relatively quickly. Portions of the software program are simulated as being executed on one model or the other according to simulation selection information (e.g., user input). State information is passed between models as the system switches from one model to another. The detailed model can comprise, for example, a “full functional” processor model, while the fast model can comprise, for example, an instruction set simulator (ISS) and a bus cycle engine (BCE). Further embodiments allow a plurality of software programs to be simulated in batch using the disclosed technologies.

Abstract: A simulation of an execution of a software program in an electronic circuit design can be analyzed to determine values simulated as being stored, such as in the memory and registers of the design, including values that are not necessarily observable on the outputs of the design. In some embodiments, a user can indicate a time period in the simulation results, or a portion of the software executable. One or more values stored in the design can be determined according to the circuit design, a description of one or more transactions of values stored in the circuit design, and one or more indications of signals provided on the outputs of the design. This can allow a user to examine values simulated as being stored in the circuit design using, for example, a software debugger showing register and memory watches. The disclosed technologies can be used with various user interface elements.

Abstract: Electronic system functionality can be initially implemented as software code (e.g., in programming languages such as C, C++ or Pascal) and selectively converted to a hardware representation such as in hardware description language (e.g., VHDL, Verilog, HandelC, BachC, SpecC and System Verilog). In one aspect, software code representations comprising memory dereferencing operations (e.g., related to pointers, arrays and structs) may also be converted to a hardware representation. The newly converted hardware representation may be given control of a main communications network (e.g., system bus) of the electronic system to control the execution of the memory dereferencing operations (e.g., related to pointers, arrays and structs). In one embodiment, bus control may be via a bus control interface adapted for a particular kind of communications network (e.g., a processor bus, a system bus, a hierarchical bus, a cross bar, a multiplexer bus, a switch network and a point to point network).

Abstract: Described herein are methods and systems for optimizing area related to hardware implementation of algorithms. The algorithms may be related to functionality of an embedded system, for instance. System functionality may be initially implemented in software and converted to hardware implementation. Prior to implementing system functionality in actual hardware, algorithms for selected system functionality or desirable all system functionality may be evaluated to determine values attained by selected variables or desirably all the variables comprised therein. In one embodiment, a probe may applied to the original software code to determine a maximum value and a minimum value corresponding to each of the variables of the algorithm (or at least one such variable) may be tracked across one or more invocations of functions (or other code components) of the algorithm comprising such variables. Based on such tracked values, a minimum size (e.g.

Abstract: A surgical table having a table top which extends between a pair of vertically extending posts and which is laterally rotatable about its longitudinal axis. The head and foot ends of the table may be raised or lowered as needed to position the patient in trendelenberg and reverse trendelenberg orientations. The table top is coupled to each of the posts by means of gimbals having perpendicular rotation axes which provide the degrees of freedom necessary to permit both lateral rotation (to any angle) and trendelenberg.

Abstract: An optimizing hardware-software co-verification system is disclosed including a number of bus interface models, a number of memory models, and a co-verification optimization manager for co-verifying a hardware-software system having memory. Co-verification is performed with a single coherent view of the memory of the hardware-software system, transparently maintained by the co-verification optimization manager for both the hardware and software verifications. This single coherent view includes at least one segment of the memory being viewed as configured for having selected portions of the segment to be statically or dynamically configured/reconfigured for either unoptimized or optimized accesses, wherein unoptimized accesses are performed through hardware verification, and optimized accesses are performed “directly” by the co-verification optimization manager, by-passing hardware verification.

Abstract: In accordance to a first aspect of the present invention, co-simulation of a hardware-software system is performed with a single coherent view of the memory of the hardware-software system. This single coherent view is transparently maintained for both the hardware and software simulations, and includes at least one segment of the memory being viewed as configured for having selected portions of the segment to be statically or dynamically configured/reconfigured for either unoptimized or optimized accesses, wherein unoptimized accesses are performed through hardware simulation, and optimized accesses are performed "directly", by-passing hardware simulation.

Abstract: An optimizing hardware-software co-simulator is constituted with a logic simulator, a number of bus interface models, a number of memory models, a number of instruction set simulators, and a co-simulation optimization manager for co-simulating a hardware-software system having memory. Co-simulation is performed with a single coherent view of the memory of the hardware-software system, transparently maintained by the co-simulation optimization manager for both the hardware and software simulations. This single coherent view includes at least one segment of the memory being viewed as configured for having selected portions of the segment to be statically or dynamically configured/reconfigured for either unoptimized or optimized accesses, wherein unoptimized accesses are performed through hardware simulation, and optimized accesses are performed "directly" by the co-simulation optimization manager, by-passing hardware simulation.