Abstract: A node controller is provided to include a first interface to interface with one or more processors, a second interface including a plurality of ports to interface with node controllers within a base node and other nodes in the cache-coherent interconnect network. The node controller can further include a third interface to interface with a first plurality of memory devices and a cache coherence management logic. The cache coherence management logic can maintain, based on a first circuitry, hardware-managed cache coherency in the cache-coherent interconnect network. The cache coherence management logic can further facilitate, based on a second circuitry, software-managed cache coherency in the cache-coherent interconnect network.

Abstract: A node controller is provided to include a first interface to interface with one or more processors, a second interface including a plurality of ports to interface with node controllers within a base node and other nodes in the cache-coherent interconnect network. The node controller can further include a third interface to interface with a first plurality of memory devices and a cache coherence management logic. The cache coherence management logic can maintain, based on a first circuitry, hardware-managed cache coherency in the cache-coherent interconnect network. The cache coherence management logic can further facilitate, based on a second circuitry, software-managed cache coherency in the cache-coherent interconnect network.

Abstract: Methods and devices for reducing the latency associated with retransmitting data packets are provided. A device used to receive data packets may include physical layer circuitry and data link layer circuitry communicatively coupled to the physical layer circuitry. The data link layer circuitry may include an Automatic Repeat reQuest (ARQ) processing circuit to send requests for retransmitting data packets. The data link layer circuitry may also include a Forward Error Correction (FEC) processing circuit to receive decoded data packets from the physical layer circuitry, to perform error correction on packets received by the physical layer circuitry, and to provide a correction status signal to the ARQ processing circuit indicating whether or not a particular decoded data packet received from the physical layer circuitry contains one or more incurable errors.

Abstract: Methods and devices for reducing the latency associated with retransmitting data packets are provided. A device used to receive data packets may include physical layer circuitry and data link layer circuitry communicatively coupled to the physical layer circuitry. The data link layer circuitry may include an Automatic Repeat reQuest (ARQ) processing circuit to send requests for retransmitting data packets. The data link layer circuitry may also include a Forward Error Correction (FEC) processing circuit to receive decoded data packets from the physical layer circuitry, to perform error correction on packets received by the physical layer circuitry, and to provide a correction status signal to the ARQ processing circuit indicating whether or not a particular decoded data packet received from the physical layer circuitry contains one or more incurable errors.

Abstract: This patent application relates generally to a shared-credit arbitration circuit for use in arbitrating access by a number of virtual channels to a shared resource managed by a destination (arbiter) based on credits allotted to each virtual channel, in which only the destination is aware of the availability of a shared pool of resources, and the destination selectively provides access to the shared pool by the virtual channels and returns credits to the source(s) associated with the virtual channels when shared resources are used so that the source(s) are unaware of the destination's use of the shared resources and are unhindered by the destination's use of shared resources. Among other things, this can significantly reduce the complexity of the source(s) and the required handshaking between the source(s) and the destination.

Abstract: This patent application relates generally to a shared-credit arbitration circuit for use in arbitrating access by a number of virtual channels to a shared resource managed by a destination (arbiter) based on credits allotted to each virtual channel, in which only the destination is aware of the availability of a shared pool of resources, and the destination selectively provides access to the shared pool by the virtual channels and returns credits to the source(s) associated with the virtual channels when shared resources are used so that the source(s) are unaware of the destination's use of the shared resources and are unhindered by the destination's use of shared resources. Among other things, this can significantly reduce the complexity of the source(s) and the required handshaking between the source(s) and the destination.

Abstract: A system for establishing a primary master node in a computer system includes a plurality of nodes, each node configured with an update interval, a hierarchy of master nodes selected from the plurality of nodes, wherein the master nodes are configured to synchronize the plurality of nodes with a clock value by sending out its clock value when its update interval has expired, wherein each node resets its update interval when it receives the clock value, a primary master node selected from the hierarchy of master nodes based on its update interval, and at least one backup master node selected from the hierarchy of master nodes based on its update interval, the backup master node configured to become the primary master node when the plurality of nodes do not receive the clock value after a predetermined period of time has elapsed.

Abstract: A system for establishing a primary master node in a computer system includes a plurality of nodes, each node configured with an update interval, a hierarchy of master nodes selected from the plurality of nodes, wherein the master nodes are configured to synchronize the plurality of nodes with a clock value by sending out its clock value when its update interval has expired, wherein each node resets its update interval when it receives the clock value, a primary master node selected from the hierarchy of master nodes based on its update interval, and at least one backup master node selected from the hierarchy of master nodes based on its update interval, the backup master node configured to become the primary master node when the plurality of nodes do not receive the clock value after a predetermined period of time has elapsed.

Abstract: A system and method of determining a master node in a computer system having a plurality of nodes includes establishing a hierarchy of master nodes from the plurality of nodes, wherein the master node synchronizes the plurality of nodes in the computer system with a clock value and determining the master node from the hierarchy of master nodes. A system and method of synchronizing a plurality of nodes in a computer system includes determining a master node from the plurality of nodes, sending a clock value from the master node to neighbor nodes of the master node, synchronizing a node clock in each node receiving the clock value if a predetermined period of time has elapsed in each receiving node, distributing a node clock value from each synchronized node to neighbor nodes of the synchronized node, and repeating synchronizing and distributing, wherein synchronizing a node clock in each node receiving the clock value includes each node receiving the node clock value.

Abstract: A system and method of determining a master node in a computer system having a plurality of nodes includes establishing a hierarchy of master nodes from the plurality of nodes, wherein the master node synchronizes the plurality of nodes in the computer system with a clock value and determining the master node from the hierarchy of master nodes. A system and method of synchronizing a plurality of nodes in a computer system includes determining a master node from the plurality of nodes, sending a clock value from the master node to neighbor nodes of the master node, synchronizing a node clock in each node receiving the clock value if a predetermined period of time has elapsed in each receiving node, distributing a node clock value from each synchronized node to neighbor nodes of the synchronized node, and repeating synchronizing and distributing, wherein synchronizing a node clock in each node receiving the clock value includes each node receiving the node clock value.