Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques directed to packages that include one or more dies that are coupled with one or more glass layers. These glass layers may be within an interposer or a patch to which the one or more dies are attached. In addition, these glass layers may be used to facilitate pitch translation between the one or more dies proximate to a first side of the glass layer and a substrate proximate to a second side of the glass layer opposite the first side, to which the one or more dies are electrically coupled. Other embodiments may be described and/or claimed.

Abstract: An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.

Abstract: A coreless substrate includes a stiffener material (110, 210, 620) having a plated via (120, 320) formed therein, an electrically insulating material (130, 230, 830) above the stiffener material, and an electrically conductive material (140, 240, 840) in the electrically insulating layer. In the same or another embodiment, a package for a microelectronic device includes a stiffener material layer (115, 215, 615) having plated vias (120, 320) formed therein and further having a recess (118, 218) therein, build-up layers (150, 350, 850) over the stiffener material layer, and a die (370) attached over the build-up layers. The stiffener material layer and the build-up layers form a coreless substrate (100, 380, 910, 920) of the package. The coreless substrate has a surface (381), and the die covers less than all of the surface of the coreless substrate such that the surface has at least one exposed region (382).

Abstract: A coreless substrate includes a stiffener material (110, 210, 620) having a plated via (120, 320) formed therein, an electrically insulating material (130, 230, 830) above the stiffener material, and an electrically conductive material (140, 240, 840) in the electrically insulating layer. In the same or another embodiment, a package for a microelectronic device includes a stiffener material layer (115, 215, 615) having plated vias (120, 320) formed therein and further having a recess (118, 218) therein, build-up layers (150, 350, 850) over the stiffener material layer, and a die (370) attached over the build-up layers. The stiffener material layer and the build-up layers form a coreless substrate (100, 380, 910, 920) of the package. The coreless substrate has a surface (381), and the die covers less than all of the surface of the coreless substrate such that the surface has at least one exposed region (382).

Abstract: A video inspection system with collimated viewing of plural containers has a conveyor for continuously transporting bodies disposed immediately adjacent one another to an inspection zone at which the bodies are backlighted. A video detector for capturing and analyzing a digital image of successive containers views the containers through a preferably fresnel collimating lens disposed between the bodies and the video detector, whereby an elevation view of the bodies is achieved. A data processing device operable to correlate the portions of successive images corresponding to a single body proceeding through the inspection zone analyzes the images and operates a downstream apparatus for segregating the bodies based upon visible features.