Patents by Inventor Russell N. Shryock

Russell N. Shryock has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Interconnect topology with staggered vias for interconnecting differential signal traces on different layers of a substrate
    Patent number: 9936570
    Abstract: An interconnect topology is disclosed that includes a plurality of interconnections, each of which is coupled together using a via, where at least two of the vias are staggered with respect to each other. In one embodiment, the interconnect topology comprises a substrate, multiple signal traces routed through the substrate on multiple layers, and a plurality of vias, where each via couples a pair of the signal traces to form an interconnection between different ones of the multiple layers, and where a pair of vias comprise a first via to carry a positive differential signal via and a second via to carry a negative differential signal that are coupled to signal traces to form a differential signal pair. The differential first and second vias are staggered with respect to each other.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: April 3, 2018
    Assignee: INTEL CORPORATION
    Inventors: Min Wang, Russell N. Shryock
  • DIFFERENTIAL INTERCONNECT TOPOLOGY IN A SUBSTRATE WITH STAGGERED VIAS
    Publication number: 20160172734
    Abstract: An interconnect topology is disclosed that includes a plurality of interconnections, each of which is coupled together using a via, where at least two of the vias are staggered with respect to each other. In one embodiment, the interconnect topology comprises a substrate, multiple signal traces routed through the substrate on multiple layers, and a plurality of vias, where each via couples a pair of the signal traces to form an interconnection between different ones of the multiple layers, and where a pair of vias comprise a first via to carry a positive differential signal via and a second via to carry a negative differential signal that are coupled to signal traces to form a differential signal pair. The differential first and second vias are staggered with respect to each other.
    Type: Application
    Filed: December 15, 2014
    Publication date: June 16, 2016
    Inventors: Min Wang, Russell N. Shryock
  • Removing ground plane resonance
    Patent number: 6861921
    Abstract: A method and apparatus for decreasing resonance in a printed circuit board (PCB) uses cuts in a ground plane to slow a signal passing through the ground plane. Cuts in the ground plane may be used alone or in conjunction with the lengthening of signal traces.
    Type: Grant
    Filed: August 27, 2003
    Date of Patent: March 1, 2005
    Assignee: Intel Corporation
    Inventors: Keith E. Dow, Russell N. Shryock
  • Cutting a ground plane to remove circuit board resonance
    Patent number: 6665927
    Abstract: A method for decreasing resonance in a printed circuit board (PCB) uses cuts in a ground plane to slow a signal passing through the ground plane. Cuts in the ground plane may be used alone or in conjunction with the lengthening of signal traces. Slowing the signal passing through the ground plane enables a mismatch between the signal transit time of the ground plane and a signal oscillation period of the circuit board to be obtained. The mismatch results in decreased resonance.
    Type: Grant
    Filed: December 29, 1999
    Date of Patent: December 23, 2003
    Assignee: Intel Corporation
    Inventors: Keith E. Dow, Russell N. Shryock