Abstract: A single chip data processor integrated circuit having an input which can be programmed to place the circuit's address and data bus terminals into one of two modes. In a first or multiplexed mode, the circuit's address and data terminals are directly connected and address bits are time division multiplexed with data bits when both are written to external circuitry. In a second or normal mode, the circuit's address and data terminals are not connected and address bits are communicated with the circuit independent of data bits which are communicated with the circuit. No circuitry external to the integrated circuit is required to implement the multiplexed mode. A control portion insures that bit collisions are avoided when the circuit is in the multiplexed mode.