Abstract: An on-chip hardware breakpoint generator is disclosed. An embodiment of the present invention is configured to monitor accesses to various memory locations and to produce a breakpoint request when a predetermined memory access occurs. The memory access being monitored can be either a memory read or a memory write. Furthermore, the memory location being monitored can be a program memory location or a data memory location. A system for carrying out the invention may include a comparator coupled to a processor. The comparator is configured to sense when a memory access to a specific location occurs. When such an access occurs, the comparator forwards a signal to a breakpoint generator to implement a breakpoint.

Abstract: A printed circuit board assembly having a first main printed circuit board and a connector connecting to the main board. A subsidiary board connects to the connector. The main board has a plurality of socket holes and the connector has a corresponding plurality of pins. The invention overcomes the problem of the prior art assembly, which requires a different main board to accommodate each type of connector having a different pin spacing. The main board of the invention has a combination group of four rows of holes, including a first row of holes and a third row of holes having a same first lengthwise spacing which receive the pins of one type of connector and including a second row of holes and a fourth row of holes having a same second lengthwise spacing which receive the pins of another type of connector. The first row of holes respectively having a first set of outer conductors. The first row of holes also respectively have a first set of inner conductors.

Abstract: An electrical circuit is described that requires a reduced number of data bits for character-address and video-mode information by using a predetermined bit combination of the video-mode information as part of the character-address information. Character-address and video-mode information is output from a random access memory (RAM) to a character read only memory (ROM) and a video-mode detection circuit that produces outputs to enable video-mode circuits in the video control circuitry. One output of the video-mode detection circuit is coupled to an address input of the character ROM that has characters divided into two character sets. A predetermined bit combination of the video-mode information produces an output from the video-mode detection circuit that selects one of the character sets while the other bit combinations produce an output from the detection circuit that selects the other character set.

Abstract: A method of comparing first and second data acquired asynchronously allows an effective comparison therebetween even if aliasing errors have occurred during acquisition thereof. Bits of the first and second data are compared in groups of three to obtain relationships therebetween. These relationships indicate if first data is equal to the second data, or the first data can be shifted right and/or left to achieve the second data. This comparison is repeated on successive groups of bits, but the comparison bits used in each data are shifted by a bit for each comparison. If any relationship indicates that the first data was shifted right (or left), then all other comparisons must indicate that the first data matches or is shifted right (or left), for the first data to be found the same as the second data. The presence of both right and left shift relationships indicates that the first and second data cannot be the same.

Abstract: Disclosed herein is a system for addressing a memory pack having a plurality of memory chips such as RAMs or ROMs. Each memory chip receives address signals and a chip enable signal. A chip selector generates the chip enable signal in response to a feedback signal from the memory pack provided in response to the memory address lines. Since each memory pack excludes the chip selector circuitry, the memory packs can be made smaller in size. The memory packs are in effect self-configuring since they control the feedback of the address signals to the chip selector which generates the chip enable signals. Many types and capacities of memory packs can be mixed in the system since the pack determines the memory address space in which it resides.

Abstract: Disclosed herein is an apparatus for displaying a logic waveform on a raster scan display device such as a CRT. A part of an input logic signal is delayed for forming a former bit, and the input logic signal acts as a present bit. A memory device stores a special pattern determined in accordance with results of logic operation of the present and former bits. An image dot of the pattern is addressed by the present and former bits and raster line position (number) information, and the output therefrom is applied as an intensity control signal to the display device. Since the memory device does not need FONT information, this invention needs very little software manipulation of data, and the capacity of the memory device is small. In addition, this invention can display glitches and graticule tick marks.