Abstract: A method for creating a non-volatile memory array includes implanting pocket implants in a substrate at least between mask columns of a given width and at least through an ONO layer covering the substrate, generating increased-width polysilicon columns from the mask columns, generating bit lines in the substrate at least between the increased-width polysilicon columns and depositing oxide at least between the polysilicon columns.

Abstract: Silicon trench isolation (STI) is formed between adjacent diffusions in a semiconductor device, such as between bitlines in a memory array. The STI may be self-aligned to the diffusions, and may prevent misaligned bitline (BL) contacts from contacting silicon outside of the corresponding bitlines. The bitline contacts may have sufficient overlap of the bitlines to ensure full coverage by the bitlines. Bitline oxides formed over buried bitlines may be used to self-align trenches of the STI to the bitlines. The STI trenches may be lined with a CMOS spacer, salicide blocking layer and/or a contact etch stop layer. STI may be formed after Poly-2 etch or after word line salicidation. The memory cells may be NVM devices such as NROM, SONOS, SANOS, MANOS, TANOS or Floating Gate (FG) devices.

Abstract: Silicon trench isolation (STI) is formed between adjacent diffusions in a semiconductor device, such as between bitlines in a memory array. The STI may be self-aligned to the diffusions, and may prevent misaligned bitline (BL) contacts from contacting silicon outside of the corresponding bitlines. The bitline contacts may have sufficient overlap of the bitlines to ensure full coverage by the bitlines. Bitline oxides formed over buried bitlines may be used to self-align trenches of the STI to the bitlines. The STI trenches may be lined with a CMOS spacer, salicide blocking layer and/or a contact etch stop layer. STI may be formed after Poly-2 etch or after word line salicidation. The memory cells may be NVM devices such as NROM, SONOS, SANOS, MANOS, TANOS or Floating Gate (FG) devices.

Abstract: A non-volatile memory array has word lines spaced a sub-F (sub-minimum feature size F) width apart and bit lines generally perpendicular to the word lines. The present invention also includes a method for word-line patterning of a non-volatile memory array which includes generating sub-F word lines from mask generated elements with widths of at least a minimum feature size F.

Abstract: A non-volatile memory array includes a multiplicity of memory cells, each of whose area is less than 4 F2 per cell (where F is a minimum feature size), and periphery elements to control the memory cells. The present invention also includes a non-volatile memory array which includes word lines and bit lines generally perpendicular to the word lines, with a word line pitch of less than 2 F. In one embodiment, the word lines are made of polysilicon spacers.

Abstract: A method for creating a non-volatile memory array includes implanting pocket implants in a substrate at least between mask columns of a given width and at least through an ONO layer covering the substrate, generating increased-width polysilicon columns from the mask columns, generating bit lines in the substrate at least between the increased-width polysilicon columns and depositing oxide at least between the polysilicon columns.

Abstract: A method for creating a non-volatile memory array includes implanting pocket implants in a substrate at least between mask columns of a given width and at least through an ONO layer covering the substrate, generating increased-width polysilicon columns from the mask columns, generating bit lines in the substrate at least between the increased-width polysilicon columns and depositing oxide at least between the polysilicon columns.

Abstract: An NVM cell such as an NROM cell is formed using a portion of one ONO stack and an adjacent portion of a neighboring NROM stack. A gate structure is formed between (and atop) the two ONO portions, or “strips” (or “stripes”). This provides having two physically separated charge storage regions (nitride “strips”, or “stripes”) in each memory cell.

Abstract: A non-volatile memory chip has word lines spaced a sub-F (sub-minimum feature size F) width apart with extensions of the word lines in at least two transition areas. Neighboring extensions are spaced at least F apart. The present invention also includes a method for word-line patterning of a non-volatile memory chip which includes generating sub-F word lines with extensions in transition areas for connecting to peripheral transistors from mask generated elements with widths of at least F.

Abstract: A non-volatile memory chip has word lines spaced a sub-F (sub-minimum feature size F) width apart with extensions of the word lines in at least two transition areas. Neighboring extensions are spaced at least F apart. The present invention also includes a method for word-line patterning of a non-volatile memory chip which includes generating sub-F word lines with extensions in transition areas for connecting to peripheral transistors from mask generated elements with widths of at least F.

Abstract: Silicon trench isolation (STI) is formed between adjacent diffusions in a semiconductor device, such as between bitlines in a memory array. The STI may be self-aligned to the diffusions, and may prevent misaligned bitline (BL) contacts from contacting silicon outside of the corresponding bitlines. The bitline contacts may have sufficient overlap of the bitlines to ensure full coverage by the bitlines. Bitline oxides formed over buried bitlines may be used to self-align trenches of the STI to the bitlines. The STI trenches may be lined with a CMOS spacer, salicide blocking layer and/or a contact etch stop layer. STI may be formed after Poly-2 etch or after word line salicidation. The memory cells may be NVM devices such as NROM, SONOS, SANOS, MANOS, TANOS or Floating Gate (FG) devices.

Abstract: A buried contact etch stop layer (CESL) is disposed between adjacent diffusions in a semiconductor device, such as between bitlines in a memory array. The CESL may be self-aligned to the diffusions, and may prevent misaligned bitline (BL) contacts from contacting silicon outside of the corresponding bitlines. The bitline contacts may have sufficient overlap of the bitlines to ensure full coverage by the bitlines. STI trenches may optionally be formed under the CESL. The CESL may comprise nitride or any other material that is harder (more resistant) to etch than the material on top of it.

Abstract: A non-volatile memory device includes a plurality of word line areas each separated from its neighbor by a contact area, an oxide-nitride-oxide (ONO) layer within the word line areas and at least partially within the contact areas and protective elements, generated when spacers are formed in the periphery area, to protect silicon under the ONO layer in the contact areas. A non-volatile memory device includes a plurality of word line areas each separated from its neighbor by a contact area and bitline oxides whose height:distance aspect ratio (T:D) is at least 25% greater than the maximum height:distance (Tg:Dg) ratio of gate electrodes in the CMOS periphery to ensure remnants of sidewall material between bitlines after sidewall spacer etch, thus protecting silicon in a subsequent word line salicidation step.

Abstract: An NVM cell such as an NROM cell is formed using a portion of one ONO stack and an adjacent portion of a neighboring NROM stack. A gate structure is formed between (and atop) the two ONO portions, or “strips” (or “stripes”). This provides having two physically separated charge storage regions (nitride “strips”, or “stripes”) in each memory cell.

Abstract: A non-volatile memory chip has word lines spaced a sub-F (sub-minimum feature size F) width apart with extensions of the word lines in at least two transition areas. Neighboring extensions are spaced at least F apart. The present invention also includes a method for word-line patterning of a non-volatile memory chip which includes generating sub-F word lines with extensions in transition areas for connecting to peripheral transistors from mask generated elements with widths of at least F.

Abstract: A non-volatile memory array includes a multiplicity of memory cells, each of whose area is less than 4 F2 per cell (where F is a minimum feature size), and periphery elements to control the memory cells. The present invention also includes a non-volatile memory array which includes word lines and bit lines generally perpendicular to the word lines, with a word line pitch of less than 2 F. In one embodiment, the word lines are made of polysilicon spacers.

Abstract: A non-volatile memory array has word lines spaced a sub-F (sub-minimum feature size F) width apart and bit lines generally perpendicular to the word lines. The present invention also includes a method for word-line patterning of a non-volatile memory array which includes generating sub-F word lines from mask generated elements with widths of at least a minimum feature size F.

Abstract: A buried bitline (BB) may be formed in at least two separate implantation steps, in addition to a pocket implant step. The pocket implant has a first width (W1) and a first depth (D1); the first BB implant has a second width (W2) defined by first sidewall spacers and a second depth (D2); the third BB implant has a third width (W3) defined by second sidewall spacers and a third depth (D3); the second width (W2) is less than the first width (W1), and the third width (W3) is less than or equal to the second width (W2); and the second depth (D2) is greater than the first depth (D1), and the third depth (D3) is greater than the second depth (D2). The first BB implant may provide for pocket implant (PI) to bitline (BL) edge optimization; and the second BB implant may provide for controlling BL resistance.

Abstract: A method for creating a non-volatile memory array includes implanting pocket implants in a substrate at least between mask columns of a given width and at least through an ONO layer covering the substrate, generating increased-width polysilicon columns from the mask columns, generating bit lines in the substrate at least between the increased-width polysilicon columns and depositing oxide at least between the polysilicon columns.

Abstract: A process for manufacturing electronic semiconductor integrated electronic memory devices having virtual ground and including at least a matrix of floating gate memory cells formed on a semiconductor substrate with a plurality of continuous bit lines extending across the substrate as discrete parallel strips begins with forming an oxide layer over the matrix region. Then, the semiconductor throughout is deposited with a stack structure which includes a first conductor layer, a first dielectric layer, and second conductor layer. Next, a second dielectric layer is formed. Floating gate regions are defined by photolithography using a mask of “POLY1 along a first predetermined direction”, and associated etching, to define, in the stack structure, a plurality of parallel openings. These openings are implanted to confer a predetermined conductivity on the bit line regions. Next, the parallel openings are filled with a photo-sensitive material to protect the matrix bit lines.