Abstract: An integrated circuit (IC) module that includes an integrated circuit (IC) package, a plurality of first solder interconnects coupled to the IC package, an interposer coupled to the IC package through the plurality of first solder interconnects a plurality of second solder interconnects coupled to the interposer; and a printed circuit board (PCB) coupled to the interposer through the plurality of second solder interconnects. The interposer includes an encapsulation layer, a first passive component at least partially embedded in the encapsulation layer, and a plurality of interconnects coupled to the first passive component. The encapsulation layer includes a mold and/or an epoxy fill. The first passive component is configured to operate as an electronic voltage regulator (EVR) for the IC module. In some implementations, the interposer is a fan out interposer.

Abstract: Some novel features pertain to an integrated device that includes a first metal layer and a second metal layer. The first metal layer includes a first set of regions. The first set of regions includes a first netlist structure for a power distribution network (PDN) of the integrated device. The second metal layer includes a second set of regions. The second set of regions includes a second netlist structure of the PDN of the integrated device. In some implementations, the second metal layer further includes a third set of regions comprising the first netlist structure for the PDN of the integrated device. In some implementations, the first metal layer includes a third set of regions that includes a third netlist structure for the PDN of the integrated device. The third set of regions is non-overlapping with the first set of regions of the first metal layer.

Abstract: A toroid inductor includes a plurality of first turns configured in a first ring shape and a plurality of second turns configured in a second ring shape. The plurality of first turns includes a plurality of first upper interconnects, a plurality of first lower interconnects, and a plurality of first vias coupled to the plurality of first upper interconnects and to the plurality of first lower interconnects. The plurality of second turns is at least partially intertwined with the plurality of first turns. The plurality of second turns includes a plurality of second upper interconnects, a plurality of second lower interconnects, and a plurality of second vias coupled to the plurality of second upper interconnects and to the plurality of second lower interconnects.

Abstract: An embedded layered inductor is provided that includes a first inductor layer and a second inductor layer coupled to the first inductor layer. The first inductor layer comprises a patterned metal layer that may also be patterned to form pads. The second inductor layer comprises metal deposited in a dielectric layer adjacent the patterned metal layer.

Abstract: Some novel features pertain to a package substrate that includes a core layer, a first via, a first dielectric layer, and a first inductor. The core layer includes a first surface and a second surface. The first via is located in the core layer. The first dielectric layer is coupled to the first surface of the core layer. The first inductor is located in the first dielectric layer. The first inductor is coupled to the first via in the core layer. The first inductor is configured to generate a magnetic field that laterally traverses the package substrate. In some implementations, the package substrate further includes a first pad coupled to the first inductor, wherein the first pad is configured to couple to a solder ball. In some implementations, the package substrate includes a second via located in the core layer, and a second inductor located in the first dielectric layer.

Abstract: A toroid inductor includes a plurality of first turns configured in a first ring shape and a plurality of second turns configured in a second ring shape. The plurality of first turns includes a plurality of first upper interconnects, a plurality of first lower interconnects, and a plurality of first vias coupled to the plurality of first upper interconnects and to the plurality of first lower interconnects. The plurality of second turns is at least partially intertwined with the plurality of first turns. The plurality of second turns includes a plurality of second upper interconnects, a plurality of second lower interconnects, and a plurality of second vias coupled to the plurality of second upper interconnects and to the plurality of second lower interconnects.

Abstract: An integrated circuit (IC) module that includes an integrated circuit (IC) package, a plurality of first solder interconnects coupled to the IC package, an interposer coupled to the IC package through the plurality of first solder interconnects a plurality of second solder interconnects coupled to the interposer; and a printed circuit board (PCB) coupled to the interposer through the plurality of second solder interconnects. The interposer includes an encapsulation layer, a first passive component at least partially embedded in the encapsulation layer, and a plurality of interconnects coupled to the first passive component. The encapsulation layer includes a mold and/or an epoxy fill. The first passive component is configured to operate as an electronic voltage regulator (EVR) for the IC module. In some implementations, the interposer is a fan out interposer.

Abstract: Some features pertain to an integrated device that includes a substrate, several metal layers coupled to the substrate, several dielectric layers coupled to the substrate, and a redistribution portion coupled to one of the metal layers. The redistribution portion includes a first metal redistribution layer, an insulation layer coupled to the first metal redistribution layer, and a second metal redistribution layer coupled to the insulation layer. The first metal redistribution layer, the insulation layer, and the second metal redistribution layer are configured to operate as a capacitor in the integrated device. In some implementations, the capacitor is a metal-insulator-metal (MIM) capacitor.

Abstract: The disclosure is related to pin layouts in a semiconductor package. One embodiment of the disclosure provides a rhombus shaped shared reference pin layout that isolates a set of differential pin pairs. The differential signal pin pairs are configured such that an axis formed by a vertical signal pin pair is orthogonal to and mutually bisecting an axis formed by a lateral signal pin pair.

Abstract: A package on package semiconductor structure includes a first package positioned above a first surface of a substrate, a second package positioned above the first package, and a first thermal element positioned between the first package and the second package, wherein the first thermal element is separated from the second package by an air gap and the thermal element provides a heat path for heat generated by the first package.

Abstract: Some novel features pertain to package substrates that include a substrate having an embedded package substrate (EPS) capacitor with equivalent series resistance (ESR) control. The EPS capacitor includes two conductive electrodes separated by a dielectric or insulative thin film material and an equivalent series resistance (ESR) control structure located on top of each electrode connecting the electrodes to vias. The ESR control structure may include a metal layer, a dielectric layer, and a set of metal pillars which are embedded in the set of metal pillars are embedded in the dielectric layer and extend between the electrode and the metal layer. The EPS capacitor having the ESR control structure form an ESR configurable EPS capacitor which can be embedded in package substrates.

Abstract: A semiconductor package for a side by side die configuration may include a substrate having a cavity, a bridge interposer positioned within the cavity and having an active side facing active sides of a first die and a second die and partially horizontally overlapping the first die and the second die to provide an interconnection between the first die and the second die, and a thermal element attached to backsides of the first die and the second die to provide a heat path and heat storage for the first die and the second die.

Abstract: Some implementations provide an integrated device that includes a capacitor and an inductor. The inductor is electrically coupled to the capacitor. The inductor and the capacitor are configured to operate as a filter for an electrical signal in the integrated device. The inductor includes a first metal layer of a printed circuit board (PCB), a set of solder balls coupled to the PCB, and a second metal layer in a die. In some implementations, the capacitor is located in the die. In some implementations, the capacitor is a surface mounted passive device on the PCB. In some implementations, the first metal layer is a trace on the PCB. In some implementations, the inductor includes a third metal layer in the die. In some implementations, the second metal layer is an under bump metallization (UBM) layer of the die, and the third metal is a redistribution layer of the die.

Abstract: Some features pertain to an integrated device (e.g., package-on-package (PoP) device) that includes a substrate, a first die, a first encapsulation layer, a first redistribution portion, a second die, a second encapsulation layer, and a second redistribution portion. The substrate includes a first surface and a second surface. The substrate includes a capacitor. The first die is coupled to the first surface of the substrate. The first encapsulation layer encapsulates the first die. The first redistribution portion is coupled to the first encapsulation. The second die is coupled to the second surface of the substrate. The second encapsulation layer encapsulates the second die. The second redistribution portion is coupled to the second encapsulation layer.

Abstract: Some novel features pertain to a semiconductor device that includes a substrate, a first cavity that traverses the substrate. The first cavity is configured to be occupied by a interconnect material (e.g., solder ball). The substrate also includes a first metal layer coupled to a first side wall of the first cavity. The substrate further includes a first integrated passive device (IPD) on a first surface of the substrate, the first IPD coupled to the first metal layer. In some implementations, the substrate is a glass substrate. In some implementations, the first IPD is one of at least a capacitor, an inductor and/or a resistor. In some implementations, the semiconductor device further includes a second integrated passive device (IPD) on a second surface of the substrate. The second IPD is coupled to the first metal layer.

Abstract: Some novel features pertain to an integrated device that includes a substrate, a first cavity through the substrate, and a toroid inductor configured around the first cavity of the substrate. The toroid inductor includes a set of windings configured around the first cavity. The set of windings includes a first set of interconnects on a first surface of the substrate, a set of though substrate vias (TSVs), and a second set of interconnects on a second surface of the substrate. The first set of interconnects is coupled to the second set of interconnects through the set TSVs. In some implementations, the integrated device further includes an interconnect material (e.g., solder ball) located within the first cavity. The interconnect material is configured to couple a die to a printed circuit board. In some implementations, the interconnect material is part of the toroid inductor.

Abstract: A package on package semiconductor structure includes a first package positioned above a first surface of a substrate, a second package positioned above the first package, and a first thermal element positioned between the first package and the second package, wherein the first thermal element is separated from the second package by an air gap and the thermal element provides a heat path for heat generated by the first package.

Abstract: An inductor design on a wafer level package (WLP) does not need to depopulate the solder balls on the die because the solder balls form part of the inductor. One terminal on the inductor couples to the die, the other terminal couples to a single solder ball on the die, and the remaining solder balls that mechanically contact the inductor remain electrically floating. The resulting device has better inductance, direct current (DC) resistance, board-level reliability (BLR), and quality factor (Q).

Abstract: Some features pertain to an integrated device (e.g., package-on-package (PoP) device) that includes a substrate, a first die, a first encapsulation layer, a first redistribution portion, a second die, a second encapsulation layer, and a second redistribution portion. The substrate includes a first surface and a second surface. The substrate includes a capacitor. The first die is coupled to the first surface of the substrate. The first encapsulation layer encapsulates the first die. The first redistribution portion is coupled to the first encapsulation. The second die is coupled to the second surface of the substrate. The second encapsulation layer encapsulates the second die. The second redistribution portion is coupled to the second encapsulation layer.

Abstract: Methods and apparatuses for reducing crosstalk. The method couples a first pin, having a first magnetic field direction, with a first socket. The method couples a second pin, having a second magnetic field direction, in a second socket. The method orients the first pin approximately orthogonally to the second pin such that the first magnetic field direction and the second magnetic field direction are approximately orthogonally oriented.