Abstract: A memory control apparatus includes a data stream format converter and a physical layer converter. The data stream format converter is configured to convert an incoming data stream that has a data stream format corresponding to a first memory type into a format-converted data stream that has a data stream format corresponding to a second memory type. The second memory type is different from the first memory type. The physical layer converter is configured to convert the format-converted data stream into a physical-layer-converted data stream that has at least one physical parameter corresponding to the second memory type. The format-converted data stream has at least one physical parameter corresponding to the first memory type.

Abstract: A memory controller capable of locating an open command cycle for the purpose of issuing a precharge packet to extreme data rate (XDR) dynamic random access memory (DRAM) devices is disclosed. In response to a receipt of two request packets concurrently, a determination is made as to whether one of the request packets includes a non-precharge command and the other one of the request packets includes a precharge command. If one of the request packets includes a non-precharge command and the other one of the request packets includes a precharge command, the request packet having a non-precharge command proceeds. In addition, the precharge command is deferred and its dynamic offset is adjusted accordingly.

Abstract: A method and apparatus for managing write-to-read turnarounds in an early read after write memory system are presented. Memory controller logic identifies a write operation's bank set, allows a different bank set read operation to issue prior to the write operation's completion, and allows a same bank set read operation to issue once the write operation completes. The memory controller includes operation counter logic, operation selection logic, operation acceptance logic, command formatting logic, and memory interface logic. The operation counter logic receives new-operation-related signals from the operation acceptance logic and, in turn, provides signals to the operation selection logic and the operation acceptance logic as to when to issue a read operation that corresponds to either an even DRAM bank or an odd DRAM bank.

Abstract: A structure of sequencers, a method, and a computer program are provided for performing initial and periodic calibrations in an XDR™ memory system. A memory controller that performs these calibrations is divided into identical, independent halves, with each half containing a Current/Impedance Calibration (i/z Cal) sequencer and six Bank sequencers. The i/z Cal sequencer contains three pathways that perform the XIO current and termination calibrations, and the XDR™ DRAM current and termination impedance calibrations. Each Bank sequencer contains normal read and write operation pathways that are reused to accomplish receive setup, receive hold, transmit setup, transmit hold, XIO receive, and XIO transmit timing calibrations. Initial and periodic calibrations are necessary to ensure the precise transfer of data between the XIOs and the XDR™ DRAMs.

Abstract: A memory controller capable of handling precharge-to-precharge restrictions is disclosed. Upon commencement of a write operation, the location of the corresponding write precharge command is tracked from a timing standpoint. A determination is then made as to whether or not a subsequent read precharge command will collide with any pending write precharge command. In a determination that a subsequent read precharge command will collide with any pending write precharge command, the issuance of this read precharge command is delayed in order to avoid any collision; also, a specific time interval between this read precharge command and subsequent read precharge commands is maintained.

Abstract: A memory controller capable of locating an open command cycle for the purpose of issuing a precharge packet to extreme data rate (XDR) dynamic random access memory (DRAM) devices is disclosed. In response to a receipt of two request packets concurrently, a determination is made as to whether one of the request packets includes a non-precharge command and the other one of the request packets includes a precharge command. If one of the request packets includes a non-precharge command and the other one of the request packets includes a precharge command, the request packet having a non-precharge command proceeds. In addition, the precharge command is deferred and its dynamic offset is adjusted accordingly.

Abstract: A method and system for using constraints to simplify a memory controller are presented. A memory controller design tool retrieves parameter ranges supported by a memory controller, and identifies troublesome parameter value combinations. The memory controller design tool suggests to 1) add logic to the memory controller to resolve the conflict, 2) incorporate a constraint that reduces/eliminates command collisions, data conflicts, and/or the need to check particular timing parameters, or 3) a combination of both. The memory controller design tool may work in conjunction with a memory controller designer to define and use the constraints.

Abstract: A method and apparatus to avoid collisions between row activate and column read or column write commands is presented. A memory controller includes control logic, activate allowed logic, and last column counter logic. The control logic sends particular values to the activate allowed logic and the last column counter logic at the beginning of a read or write operation, such as a new command load value, a read count value, and a write count value. In turn, the control logic receives an activate allowed signal from the activate allowed logic, which indicates the times at which a new activate command may be issued. As a result, the memory controller allows an activate command to commence on “even” command cycles or anytime after the last outstanding column command has been issued.

Abstract: A method and apparatus for managing write-to-read turnarounds in an early read after write memory system are presented. Memory controller logic identifies a write operation's bank set, allows a different bank set read operation to issue prior to the write operation's completion, and allows a same bank set read operation to issue once the write operation completes. The memory controller includes operation counter logic, operation selection logic, operation acceptance logic, command formatting logic, and memory interface logic. The operation counter logic receives new-operation-related signals from the operation acceptance logic and, in turn, provides signals to the operation selection logic and the operation acceptance logic as to when to issue a read operation that corresponds to either an even DRAM bank or an odd DRAM bank.

Abstract: A method, a computer program, and an apparatus are provided for flexible SC to SR mapping to enable sub-page activation in an XDR™ memory system. An XDR™ memory system may allow system page size to reduced by a factor of two (half-page activation) or four (quarter-page activation). In an XDR™ memory system there are five different SCs and two different SRs. This scheme allows any one of the five SCs (or none) to be mapped to any one of the two SRs. Overall, this invention provides a flexible mapping scheme that can be utilized for any possible XDR memory system.

Abstract: A method, an apparatus, and a computer program are provided to control refreshes in Extreme Data Rate (XDR™) memory systems. XDR™ memory systems employ calibrations to ensure the precise transmission of data. During calibrations, memory refreshes can occur; however, these refreshes can interfere with calibration streams. Therefore, to alleviate collisions and interferences, refreshes are deferred to periods where no calibrations are taking place. The number of deferred refreshes is also tracked such that the overall loss of refreshes is prevented.

Abstract: A structure of sequencers, a method, and a computer program are provided for performing initial and periodic calibrations in an XDR™ memory system. A memory controller that performs these calibrations is divided into identical, independent halves, with each half containing a Current/Impedance Calibration (i/z Cal) sequencer and six Bank sequencers. The i/z Cal sequencer contains three pathways that perform the XIO current and termination calibrations, and the XDR™ DRAM current and termination impedance calibrations. Each Bank sequencer contains normal read and write operation pathways that are reused to accomplish receive setup, receive hold, transmit setup, transmit hold, XIO receive, and XIO transmit timing calibrations. Initial and periodic calibrations are necessary to ensure the precise transfer of data between the XIOs and the XDR™ DRAMs.