Abstract: Systems, apparatuses, and methods for implementing a periodic receiver clock data recovery scheme with dynamic data edge paths are disclosed. An IQ link calibration scheme performs a non-destructive data and edge path switch to determine an IQ offset without disturbing the data. A data path and an edge path pass through multiple stages of deserializers to widen the data path, with the deserializers clocked by clock divided versions of the original data and edge clocks. To initiate a calibration routine, the edge clock is aligned with the data clock, and then data and edge paths are swapped at a common point in a slower clock domain. The data path is then calibrated while the edge path carries the data signal. After the data path is calibrated, the edge and data paths are swapped back to the original configuration.

Abstract: According to one general aspect, an apparatus may include an instruction fetch unit circuit configured to retrieve instructions from a memory. The apparatus may include an instruction decode unit configured to convert instructions into one or more micro-operations that are provided to an execution unit circuit. The apparatus may also include a micro-operation cache configured to store micro-operations. The apparatus may further include a branch prediction circuit configured to: determine when a kernel of instructions is repeating, store at least a portion of the kernel within the micro-operation cache, and provide the stored portion of the kernel to the execution unit circuit without the further aid of the instruction decode unit circuit.

Abstract: According to one general aspect, an apparatus may include an instruction fetch unit circuit configured to retrieve instructions from a memory. The apparatus may include an instruction decode unit configured to convert instructions into one or more micro-operations that are provided to an execution unit circuit. The apparatus may also include a micro-operation cache configured to store micro-operations. The apparatus may further include a branch prediction circuit configured to: determine when a kernel of instructions is repeating, store at least a portion of the kernel within the micro-operation cache, and provide the stored portion of the kernel to the execution unit circuit without the further aid of the instruction decode unit circuit.

Abstract: A memory loopback system and method including an address/command transmit source configured to transmit a command and associated address through an address/command path. A transmit data source is configured to transmit write data associated with the command through a write path. Test control logic is configured to generate gaps between successive commands. A loopback connection is configured to route the write data from the write path to a read path. A data comparator is configured to compare the data received via the read path to a receive data source and generate a data loopback status output. Pattern generation logic can be configured to generate a loopback strobe, the loopback strobe being coupled to the read path. The pattern generation logic may be configured to synthesize a read strobe based on the test control logic and to use the synthesized read strobe as the loopback strobe.

Abstract: A shared memory controller and method of operation are provided. The shared memory controller is configured for use with a plurality of processors such as a central processing unit or a graphics processing unit. The shared memory controller includes a command queue configured to hold a plurality of memory commands from the plurality of processors, each memory command having associated priority information. The shared memory controller includes boost logic configured to identify a latency sensitive memory command and update the priority information associated with the memory command to identify the memory command as latency sensitive. The boost logic may be configured to identify a latency sensitive processor command. The boost logic may be configured to track time duration between successive latency sensitive memory commands.

Abstract: A method and apparatus of alternating service modes of a silicon on insulator (SOI) process circuit includes determining whether the SOI process circuit is in a first or second service mode. A first clock or a second clock is selected for transmission along a buswire of the SOI process circuit based upon the determination. A receiving device of the signal is notified whether the SOI process circuit is operating in the first service mode or the second service mode.

Abstract: A method and apparatus for generating a clock that can be switched in phase within a reduced interval of dead time are disclosed.

Abstract: A method and apparatus for generating a clock that can be switched in phase within a reduced interval of dead time are disclosed.

Abstract: A memory loopback system and method including an address/command transmit source configured to transmit a command and associated address through an address/command path. A transmit data source is configured to transmit write data associated with the command through a write path. Test control logic is configured to generate gaps between successive commands. A loopback connection is configured to route the write data from the write path to a read path. A data comparator is configured to compare the data received via the read path to a receive data source and generate a data loopback status output. Pattern generation logic can be configured to generate a loopback strobe, the loopback strobe being coupled to the read path. The pattern generation logic may be configured to synthesize a read strobe based on the test control logic and to use the synthesized read strobe as the loopback strobe.

Abstract: A method and apparatus of alternating service modes of a silicon on insulator (SOI) process circuit includes determining whether the SOI process circuit is in a first or second service mode. A first clock or a second clock is selected for transmission along a buswire of the SOI process circuit based upon the determination. A receiving device of the signal is notified whether the SOI process circuit is operating in the first service mode or the second service mode.

Abstract: A device for implementing transaction ordering enforcement between different queues of a computer system interconnect using an inter-queue ordering mechanism. The device includes first and second circular queues and input and output counters. The queues have an ordering dependency requirement between them such that entries in the second queue are not allowed to pass entries in the first queue. One requirement is that an entry in the second queue cannot be dequeued before an entry that was placed earlier in the first queue is dequeued. Another requirement is that an entry in the second queue cannot be dequeued before an entry that was placed earlier in the first queue is dequeued and then acknowledged as completed. The input and the output counters increment whenever an entry is enqueued to or dequeued from the first queue, respectively. The device may be implemented PCI and PCI-X systems or other interconnect systems.

Abstract: A method and architecture optimizes transaction ordering in a hierarchical bridge environment. A parent-bridge is one level above a child-bridge, which in turn is one level above a grand-child component. The parent-bridge is a bridge-bridge. The child-bridge can be a bus-bridge or a bridge-bridge. The grand-child component can be a bus, a bus-bridge or a bridge-bridge. A parent-bridge is connected to a child-bridge via child-links, the child-bridge connected to grandchild-links, and the parent-bridge having multiple transaction order queues (TOQs) per child-link. Ideally, the parent-bridge has one TOQ for each grandchild-link where the parent-bridge applies separate transaction ordering for each of the grandchild-links. However, at a minimum, the system uses at least two TOQs per child-link, and as such, provides a higher level of transaction throughput than systems using one TOQ per child-link. The child-bridge sends a signal to the parent-bridge identifying from which grandchild-link a transaction was sent.

Abstract: A system allows queuing interconnect transactions of a first transaction type and a second transaction type according to an interconnect protocol for a computer system with multiple nodes in a transaction order queue (TOQ). Interconnect transactions are dequeued from the TOQ and scheduled for a destination node through a buffer between the TOQ and a scheduler. Interconnect transactions of the first transaction type are blocked from the scheduler until all interconnect transactions scheduled for other nodes in the computer system have completed. No interconnect transactions are dequeued from the TOQ while an interconnect transactions of the first transaction type is blocked from the scheduler. The queuing technique imposes an additional ordering on interconnect transactions in addition to ordering rules of the interconnect protocol.

Abstract: A technique is disclosed for facilitating data processing in a computer system. The technique utilizes logic to implement a dual mode design for PCI/PCI-X computer systems that enables optimal efficiency in regardless of which mode the system is operating in. The technique involves the implementation of two sets of transmitting and receiving elements, one tuned to PCI protocol timing and the other to PCI-X protocol. Therefore, allowing the system to process both PCI and PCI-X transactions without adversely affecting the other functional mode. The technique also enables an operator to adjust the clock timing separately for each protocol without having a detrimental affect on the other operating protocol.

Abstract: A system allows queuing interconnect transactions of a first transaction type and a second transaction type according to an interconnect protocol for a computer system in a transaction order queue (TOQ). The queuing technique imposes an additional ordering on interconnect transactions in addition to ordering rules of the interconnect protocol. Transactions can bypass the TOQ if no transactions of the first type are awaiting execution or are in the TOQ. Transactions are dequeued from the TOQ if no transactions of either the first transaction type or the second transaction type are awaiting scheduling for execution.

Abstract: A system allows queuing interconnect transactions of a first transaction type and a second transaction type according to an interconnect protocol for a computer system with multiple nodes in a transaction order queue (TOQ). Interconnect transactions are dequeued from the TOQ and scheduled for a destination node through a buffer between the TOQ and a scheduler. Interconnect transactions of the first transaction type are blocked from the scheduler until all interconnect transactions scheduled for other nodes in the computer system have completed. No interconnect transactions are dequeued from the TOQ while an interconnect transactions of the first transaction type is blocked from the scheduler. The queuing technique imposes an additional ordering on interconnect transactions in addition to ordering rules of the interconnect protocol.

Abstract: A system allows queuing interconnect transactions of a first transaction type and a second transaction type according to an interconnect protocol for a computer system in a transaction order queue (TOQ). The queuing technique imposes an additional ordering on interconnect transactions in addition to ordering rules of the interconnect protocol. Transactions can bypass the TOQ if no transactions of the first type are awaiting execution or are in the TOQ. Transactions are dequeued from the TOQ if no transactions of either the first transaction type or the second transaction type are awaiting scheduling for execution.

Abstract: A device for implementing transaction ordering enforcement between different queues of a computer system interconnect using an inter-queue ordering mechanism. The device includes first and second circular queues and input and output counters. The queues have an ordering dependency requirement between them such that entries in the second queue are not allowed to pass entries in the first queue. One requirement is that an entry in the second queue cannot be dequeued before an entry that was placed earlier in the first queue is dequeued. Another requirement is that an entry in the second queue cannot be dequeued before an entry that was placed earlier in the first queue is dequeued and then acknowledged as completed. The input and the output counters increment whenever an entry is enqueued to or dequeued from the first queue, respectively. The device may be implemented PCI and PCI-X systems or other interconnect systems.

Abstract: A method and architecture optimizes transaction ordering in a hierarchical bridge environment. A parent-bridge is one level above a child-bridge, which in turn is one level above a grand-child component. The parent-bridge is a bridge-bridge. The child-bridge can be a bus-bridge or a bridge-bridge. The grand-child component can be a bus, a bus-bridge or a bridge-bridge. A parent-bridge is connected to a child-bridge via child-links, the child-bridge connected to grandchild-links, and the parent-bridge having multiple transaction order queues (TOQs) per child-link. Ideally, the parent-bridge has one TOQ for each grandchild-link where the parent-bridge applies separate transaction ordering for each of the grandchild-links. However, at a minimum, the system uses at least two TOQs per child-link, and as such, provides a higher level of transaction throughput than systems using one TOQ per child-link. The child-bridge sends a signal to the parent-bridge identifying from which grandchild-link a transaction was sent.

Abstract: A technique is disclosed for facilitating data processing in a computer system. The technique utilizes logic to implement a dual mode design for PCI/PCI-X computer systems that enables optimal efficiency in regardless of which mode the system is operating in. The technique involves the implementation of two sets of transmitting and receiving elements, one tuned to PCI protocol timing and the other to PCI-X protocol. Therefore, allowing the system to process both PCI and PCI-X transactions without adversely affecting the other functional mode. The technique also enables an operator to adjust the clock timing separately for each protocol without having a detrimental affect on the other operating protocol.