Patents by Inventor Ryan James Goss

Ryan James Goss has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Multi-tiered memory with different metadata levels
    Patent number: 9552288
    Abstract: Method and apparatus for managing data in a memory. In accordance with some embodiments, a data object is stored in a first non-volatile tier of a multi-tier memory structure. A metadata unit is generated to describe the data object, the metadata unit having a selected granularity. The metadata unit is stored in a different, second non-volatile tier of the multi-tier memory structure responsive to the selected granularity.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: January 24, 2017
    Assignee: Seagate Technology LLC
    Inventors: Ryan James Goss, Mark Allen Gaertner, Michael Joseph Steiner
  • Layered architecture for hybrid controller
    Patent number: 9529724
    Abstract: Approaches for implementing a controller for a hybrid memory that includes a main memory and a cache for the main memory are discussed. The controller comprises a hierarchy of abstraction layers, wherein each abstraction layer is configured to provide at least one component of a cache management structure. Each pair of abstraction layers utilizes processors communicating through an application programming interface (API). The controller is configured to receive incoming memory access requests from a host processor and to manage outgoing memory access requests routed to the cache using the plurality of abstraction layers.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: December 27, 2016
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Sumanth Jannyavula Venkata, James David Sawin, Yunaldi Yulizar, Ryan James Goss
  • Command execution using existing address information
    Patent number: 9507710
    Abstract: Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, a memory module has a plurality of solid-state non-volatile memory cells. A controller communicates a first command having address information and a first operation code. The first operation code identifies a first action to be taken by the memory module in relation to the address information. The controller subsequently communicates a second command having a second operation code without corresponding address information. The memory module takes a second action identified by the second command using the address information from the first command.
    Type: Grant
    Filed: May 4, 2015
    Date of Patent: November 29, 2016
    Assignee: Seagate Technology LLC
    Inventors: Kris Conklin, Bruce Dunlop, Mark Allen Gaertner, Ryan James Goss
  • Selecting between non-volatile memory units having different minimum addressable data unit sizes
    Patent number: 9489148
    Abstract: An apparatus includes a controller capable of being coupled to a host interface and a memory device. The memory device includes two or more non-hierarchical, non-volatile memory units having different minimum addressable data unit sizes. The controller is configured to at least perform determining a workload indicator of a data object being stored in the memory device via the host interface. The controller selects one of the memory units in response to the workload indicator of the data object corresponding to the minimum addressable data unit size of the selected memory unit corresponding to the workload indicator. The data object is stored in the selected memory unit in response thereto.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: November 8, 2016
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Ryan James Goss, Jon D. Trantham, Antoine Khoueir, David Scott Ebsen, Mark Allen Gaertner, Kevin Gomez
  • Non-volatile buffering to enable sloppy writes and fast write verification
    Patent number: 9424946
    Abstract: Method and apparatus for managing data in a memory. In accordance with some embodiments, input write data having a selected logical address are stored in a rewriteable non-volatile (NV) buffer. A copy of the input write data is transferred to an NV main memory using a sloppy write process. A verify operation is subsequently performed to verify successful transfer of the copy of the input write data to the NV main memory using a hash value generated responsive to the input write data in the NV buffer.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: August 23, 2016
    Assignee: Seagate Technology LLC
    Inventors: Kevin Arthur Gomez, Michael Joseph Steiner, Mark Allen Gaertner, Ryan James Goss
  • Metadata journaling with error correction redundancy
    Patent number: 9411717
    Abstract: Method and apparatus for managing a memory, such as but not limited to a flash memory. In accordance with some embodiments, user data and associated metadata are stored in a memory. The metadata are arranged as a first sequence of snapshots of the metadata at different points in time during the operation of the memory, and a second sequence of intervening journals which reflect updates to the metadata from one snapshot to the next. Requested portions of the metadata are recovered from the memory using a selected snapshot in the first sequence and first and second journals in the second sequence.
    Type: Grant
    Filed: October 23, 2012
    Date of Patent: August 9, 2016
    Assignee: Seagate Technology LLC
    Inventors: Ryan James Goss, David Scott Seekins, Mark Allen Gaertner
  • Assigning a weighting to host quality of service indicators
    Patent number: 9367262
    Abstract: Quality of service indicators are provided from a host via a host interface. The quality of service indicators relate to data stored in a non-volatile data storage via the host. Workload indicators related to the quality of service indicators are measured, and a weighting is assigned to the host in response to a correlation between the quality of service indicators and the measured workload indicators. The weighting is applied to the quality of service indicators when responding to data access requests from the host.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: June 14, 2016
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Ryan James Goss, Michael Joseph Steiner, Mark Allen Gaertner, David Scott Ebsen
  • Methods and apparatuses using a transfer function to predict resistance shifts and/or noise of resistance-based memory
    Patent number: 9349444
    Abstract: Two or more workload indicators affecting a memory cell of a resistance-based, non-volatile memory are measured. The two or more workload indicators are applied to a transfer function that predicts a resistance shift and/or resistance noise variance in response to the two or more workload indicators. A result of the transfer function is applied to shift and/or determine a threshold resistance used for at least one of a program operation and a read operation affecting the memory cell. An error rate of the memory cell is reduced as a result.
    Type: Grant
    Filed: January 13, 2015
    Date of Patent: May 24, 2016
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Ara Patapoutian, Ryan James Goss, Antoine Khoueir
  • PERFORMING MATHEMATICAL OPERATIONS ON CHANGED VERSIONS OF DATA OBJECTS VIA A STORAGE COMPUTE DEVICE
    Publication number: 20160098431
    Abstract: A data object is received from a host and stored on a storage compute device. A first mathematical operation is performed on the data object via the storage compute device. An update from the host is received and stored on the storage compute device. The update data is stored separately from the data object and includes a portion of the data object that has subsequently changed. A second mathematical operation is performed on a changed version of the data object using the update data.
    Type: Application
    Filed: October 6, 2014
    Publication date: April 7, 2016
    Inventors: David Scott Ebsen, Ryan James Goss, Jeffrey L. Whaley, Dana Simonson
  • DYNAMICALLY MODIFYING A BOUNDARY OF A DEEP LEARNING NETWORK
    Publication number: 20160098646
    Abstract: A connection between a user device and a network server is established. Via the connection, a deep learning network is formed for a processing task. A first portion of the deep learning network operates on the user device and a second portion of the deep learning network operates on the network server.
    Type: Application
    Filed: October 6, 2014
    Publication date: April 7, 2016
    Inventors: Kevin Arthur Gomez, Frank Dropps, Ryan James Goss, Jon Trantham, Antoine Khoueir
  • POWER MANAGEMENT IN A STORAGE COMPUTE DEVICE
    Publication number: 20160085291
    Abstract: Computations are performed on data objects via two or more data storage sections. The data storage sections facilitate persistently storing the data objects in parallel read/write operations. The data objects are used in computations within a storage compute device. At least one of the storage sections is deactivated during the computations to reduce power usage of the storage compute device.
    Type: Application
    Filed: September 24, 2014
    Publication date: March 24, 2016
    Inventors: David Scott Ebsen, Ryan James Goss, Jeffrey L. Whaley, Dana Simonson
  • MANAGING RESOURCE COLLISIONS IN A STORAGE COMPUTE DEVICE
    Publication number: 20160077885
    Abstract: A storage compute device includes a data storage section that facilitates persistently storing host data as data objects. The storage compute device also includes two or more compute sections that perform computations on the data objects. A controller monitors resource collisions affecting a first of the compute sections.
    Type: Application
    Filed: September 15, 2014
    Publication date: March 17, 2016
    Inventors: David Scott Ebsen, Ryan James Goss, Jeffrey L. Whaley, Dana Simonson
  • SELECTIVE COMPRESSION OF OBJECTS IN A STORAGE COMPUTE DEVICE
    Publication number: 20160078045
    Abstract: Methods and apparatuses facilitate receiving a command via a host interface of a storage compute device to perform a computation on one or more data objects. The computations producing intermediate objects that are stored in data storage section of the storage compute device. A determination is made to compress and decompress the intermediate objects as they are moved between the data storage section and a compute section based on wear of a storage medium being reduced in response to the compression and decompression. The intermediate objects are compressed and decompressed as they are moved between the data storage section and the compute section in response to the determination.
    Type: Application
    Filed: September 15, 2014
    Publication date: March 17, 2016
    Inventors: David Scott Ebsen, Ryan James Goss, Jeffrey L. Whaley, Dana Simonson
  • ASSOCIATING KEYS WITH DATA AND COMPUTE OBJECTS IN A STORAGE COMPUTE DEVICE
    Publication number: 20160077978
    Abstract: A definition is received of at least one data object and a compute object from a host at a storage compute device. A first key is associated with the at least one data object and a second key is associated with the compute object. A command is received from the host to perform a computation that links the first and second keys. The computation is defined by the compute object and acts on the data object. The computation is performed via the storage compute device using the compute object and the data object in response to the command.
    Type: Application
    Filed: September 15, 2014
    Publication date: March 17, 2016
    Inventors: David Scott Ebsen, Ryan James Goss, Jeffrey L. Whaley, Dana Simonson
  • COMBINING DATA BLOCKS IN A NON-VOLATILE, SOLID-STATE MEMORY
    Publication number: 20160054940
    Abstract: First and second data representation are stored in first and second blocks of a non-volatile, solid-state memory. The first and second blocks share series-connected bit lines. The first and second blocks are selected and other blocks of the non-volatile, solid-state memory that share the bit lines are deselected. The bit lines are read to determine a combination of the first and second data representations. The combination may include a union or an intersection.
    Type: Application
    Filed: August 22, 2014
    Publication date: February 25, 2016
    Inventors: Antoine Khoueir, Ryan James Goss, Jon Trantham, Kevin Gomez, Frank Dropps
  • Variable data recovery scheme hierarchy
    Patent number: 9244766
    Abstract: Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, a memory has a plurality of solid-state non-volatile memory cells. A processing circuit is connected to the memory and configured to direct the execution of a plurality of read error recovery routines in response to at least one uncorrectable read error in a data set retrieved from the memory. The recovery routines are executed in a selected order based on an elapsed recovery time parameter for each of the recovery routines and an estimated probability of success of each of the recovery routines.
    Type: Grant
    Filed: September 23, 2013
    Date of Patent: January 26, 2016
    Assignee: Seagate Technology LLC
    Inventors: Ara Patapoutian, Bruce Douglas Buch, Ryan James Goss, Mark Allen Gaertner, Arvind Sridharan
  • Memory device with variable code rate
    Patent number: 9201728
    Abstract: Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, the apparatus has a solid-state non-volatile memory and a processing circuit configured to write data to a selected location of the memory. The data are arranged in the form of multi-bit code words each comprising a user data payload and associated parity data configured to correct one or more bit errors in the user data payload. The processing circuit adjusts at least a selected one of a size of the code words, a size of the user data payloads or a size of the parity data responsive to at least a selected one of an accumulated count of access operations upon the selected location or an error rate associated with the selected location.
    Type: Grant
    Filed: September 12, 2013
    Date of Patent: December 1, 2015
    Assignee: Seagate Technology LLC
    Inventors: Ara Patapoutian, Ryan James Goss, Mark Allen Gaertner, Bruce Douglas Buch, Arvind Sridharan
  • ECC management for variable resistance memory cells
    Patent number: 9164832
    Abstract: A data storage device may generally be constructed and operated with at least a controller configured to identify a variance from a predetermined threshold in at least one variable resistance memory cell and upgrade a first error correction code (ECC) level to a second ECC level for the at least one variable resistance memory cell.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: October 20, 2015
    Assignee: Seagate Technology LLC
    Inventors: Mark Allen Gaertner, Ryan James Goss, Antoine Khoueir, Ara Patapoutian
  • Transfer unit management
    Patent number: 9164837
    Abstract: Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, a non-volatile memory is arranged into a plurality of blocks, with each of the blocks constituting an integral plural number N of fixed-sized, multi-bit transfer units. A processing circuit retrieves at least a portion of the data stored in a selected block to a volatile memory buffer in response to a transfer unit (TU) bit map. The TU bit map is stored in a memory and provides a multi-bit sequence of bits corresponding to the N transfer units of the selected block. The values of the bits in the multi-bit sequence of bits indicate whether the corresponding transfer units are to be retrieved.
    Type: Grant
    Filed: September 12, 2013
    Date of Patent: October 20, 2015
    Assignee: Seagate Technology LLC
    Inventors: Mark Allen Gaertner, Bruce Douglas Buch, Ryan James Goss
  • Methods and devices to increase memory device data reliability
    Patent number: 9164830
    Abstract: A first data set is written to first memory units identified as having a higher data reliability and a second data set is written to second memory units identified as having a lower data reliability than the first memory units. In some cases, the second data set may include metadata or redundancy information that is useful to aid in reading and/or decoding the first data set. The act of writing the second data set increases the data reliability of the first data set. The second data set may be a null pattern, such as all erased bits.
    Type: Grant
    Filed: January 14, 2014
    Date of Patent: October 20, 2015
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Navneeth Kankani, Mark Allen Gaertner, Rodney Virgil Bowman, Ryan James Goss, David Scott Seekins, Tong Shirh Stone