Patents by Inventor Ryan James Kier
Ryan James Kier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9071270Abstract: A time-interleaved Analog-to-Digital Converter (ADC) includes a set of time multiplexed sub-ADC circuits, each sub-ADC circuit comprising a sample-and-hold circuit. Each sample-and-hold circuit includes a bootstrap circuit for maintaining a constant voltage level between an input terminal of a switch and a gate terminal of the switch, the switch for switching between a track mode and a hold mode, and a capacitor bank associated with the bootstrap circuit such that a setting of the capacitor bank affects the voltage level.Type: GrantFiled: May 31, 2013Date of Patent: June 30, 2015Assignee: CREST SEMICONDUCTORS, INC.Inventors: Tracy Johancsik, Ryan James Kier, Yusuf Haque
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Patent number: 8890739Abstract: A time interleaving Analog-to-Digital Converter (ADC) comprises a plurality of ADCs; a timing generator that generates a clock signal for each of the ADCs such that edges of said clock signals trigger sampling of an input signal by the ADCs; and a timing adjustment circuit to receive and adjust the clock signals before the clock signals are received by the ADCs such that samplings of said input signal are spaced in time and occur at a rate of 1/N times a desired sampling rate; and circuit for adjusting the bandwidth of the plurality of ADCs.Type: GrantFiled: December 5, 2012Date of Patent: November 18, 2014Assignee: Crest Semiconductors, Inc.Inventors: Donald E. Lewis, Ryan James Kier, Rex K. Hales, Yusuf Haque
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Patent number: 8890729Abstract: A time interleaving Analog-to-Digital Converter (ADC) comprises a plurality of ADCs; a timing generator that generates a dock signal for each of the plurality of ADCs such that edges of said clock signals trigger sampling of an input signal by the plurality of ADCs; and a timing adjustment circuit to receive and adjust the dock signals before the dock signals are received by the ADCs such that samplings of said input signal are spaced in time and occur at a rate of 1/N times a desired sampling rate; and a random number generator to pseudo randomly select which ADC samples the input signal; and a circuit for adjusting the bandwidth of the plurality of ADCs.Type: GrantFiled: January 26, 2013Date of Patent: November 18, 2014Assignee: Crest Semiconductors, Inc.Inventors: Donald E. Lewis, Ryan James Kier, Rex K. Hales, Yusuf A. Haque
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Publication number: 20140152477Abstract: A time interleaving Analog-to-Digital Converter (ADC) comprises a plurality of ADCs; a timing generator that generates a clock signal for each of the ADCs such that edges of said clock signals trigger sampling of an input signal by the ADCs; and a timing adjustment circuit to receive and adjust the clock signals before the clock signals are received by the ADCs such that samplings of said input signal are spaced in time and occur at a rate of 1/N times a desired sampling rate; and circuit for adjusting the bandwidth of the plurality of ADCs.Type: ApplicationFiled: December 5, 2012Publication date: June 5, 2014Applicant: CREST SEMICONDUCTORS, INC.Inventors: Donald E. Lewis, Ryan James Kier, Rex K. Hales, Yusuf Haque
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Publication number: 20140152478Abstract: A time interleaving Analog-to-Digital Converter (ADC) comprises a plurality of ADCs; a timing generator that generates a dock signal for each of the plurality of ADCs such that edges of said clock signals trigger sampling of an input signal by the plurality of ADCs; and a timing adjustment circuit to receive and adjust the dock signals before the dock signals are received by the ADCs such that samplings of said input signal are spaced in time and occur at a rate of 1/N times a desired sampling rate; and a random number generator to pseudo randomly select which ADC samples the input signal; and a circuit for adjusting the bandwidth of the plurality of ADCs.Type: ApplicationFiled: January 26, 2013Publication date: June 5, 2014Applicant: CREST SEMICONDUCTORS, INC.Inventors: Donald E. Lewis, Ryan James Kier, Rex K. Hales, Yusuf A. Haque
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Publication number: 20130265182Abstract: A time-interleaved Analog-to-Digital Converter (ADC) includes a set of time multiplexed sub-ADC circuits, each sub-ADC circuit comprising a sample-and-hold circuit. Each sample-and-hold circuit includes a bootstrap circuit for maintaining a constant voltage level between an input terminal of a switch and a gate terminal of the switch, the switch for switching between a track mode and a hold mode, and a capacitor bank associated with the bootstrap circuit such that a setting of the capacitor bank affects the voltage level.Type: ApplicationFiled: May 31, 2013Publication date: October 10, 2013Inventors: Tracy Johancsik, Ryan James Kier, Yusuf Haque
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Patent number: 8542143Abstract: A pipelined Analog-to-Digital Converter (ADC) stage includes a main sampling path having a first filter in series with a first sample and hold circuit and a sub-ADC sampling path having a second filter in series with a second sample and hold circuit driving a sub-ADC connected to a sub-Digital-to-Analog Converter (DAC). The frequency response of the main sampling path is matched to a frequency response of the sub-ADC sampling path such that a residue signal of the pipelined ADC stage stays within range.Type: GrantFiled: March 6, 2012Date of Patent: September 24, 2013Assignee: Crest Semiconductors, Inc.Inventors: Yusuf Haque, Ryan James Kier, Rex K. Hales, Paul Talmage Watkins, Marcellus C. Harper
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Publication number: 20130234870Abstract: A pipelined Analog-to-Digital Converter (ADC) stage includes a main sampling path having a first filter in series with a first sample and hold circuit and a sub-ADC sampling path having a second filter in series with a second sample and hold circuit driving a sub-ADC connected to a sub-Digital-to-Analog Converter (DAC). The frequency response of the main sampling path is matched to a frequency response of the sub-ADC sampling path such that a residue signal of the pipelined ADC stage stays within range.Type: ApplicationFiled: March 6, 2012Publication date: September 12, 2013Applicant: CREST SEMICONDUCTORS, INCInventors: Yusuf Haque, Ryan James Kier, Rex K. Hales, Paul Talmage Watkins, Marcellus C. Harper
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Patent number: 8525596Abstract: A reference buffer amplifier within an integrated circuit includes a first output terminal connected to a first bond pad, the first bond pad being connected to a first external pin of the integrated circuit chip, the first external pin to allow an external capacitance to be connected to the output terminal. The reference buffer further includes a variable, settable resistance sub-circuit connected to a second bond pad, the second bond pad also being connected to the first external pin. The resistance sub-circuit is configured to be set to exhibit a resistance value to critically dampen a response of the reference buffer amplifier.Type: GrantFiled: November 11, 2011Date of Patent: September 3, 2013Assignee: Crest Semiconductors, Inc.Inventors: Tracy Johancsik, Rex K. Hales, Ryan James Kier, Yusuf Haque
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Patent number: 8497790Abstract: A pipelined Analog-to-Digital Converter (ADC) includes circuitry to characterize capacitors associated with a Multiplying-Digital-to-Analog Converter (MDAC) of a stage of said pipelined ADC, said capacitors contributing to a gain of said pipelined ADC, circuitry to connect a subset of said capacitors not currently being characterized to reference signals of said pipelined ADC such that a residue signal of said stage stays within an input range of an instrument measuring said residue signal, circuitry to calculate said gain of said pipelined ADC using said capacitor characterizations, and an output adjusting component to digitally change an output of said pipelined ADC to compensate for said calculated gain.Type: GrantFiled: March 20, 2012Date of Patent: July 30, 2013Assignee: Crest Semiconductors, Inc.Inventors: Donald E. Lewis, Ryan James Kier, Paul Talmage Watkins, Rex K. Hales, Yusuf Haque
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Patent number: 8466818Abstract: A time-interleaved Analog-to-Digital Converter (ADC) includes a set of sub-ADC circuits. Each sub-ADC circuit comprises a sample-and-hold circuit. Each sample-and-hold circuit includes a bootstrap circuit for maintaining a constant voltage level between an input terminal of a switch and a gate terminal of the switch, the switch for switching between a sample mode and a hold mode. Each sample and hold circuit also includes a capacitor bank associated with the bootstrap circuit such that a setting of the capacitor bank affects an ON state intrinsic resistance of the switch by affecting the voltage level.Type: GrantFiled: December 1, 2011Date of Patent: June 18, 2013Assignee: Crest Semiconductors, Inc.Inventors: Tracy Johancsik, Ryan James Kier, Yusuf Haque
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Publication number: 20130141261Abstract: A time-interleaved Analog-to-Digital Converter (ADC) includes a set of sub-ADC circuits. Each sub-ADC circuit comprises a sample-and-hold circuit. Each sample-and-hold circuit includes a bootstrap circuit for maintaining a constant voltage level between an input terminal of a switch and a gate terminal of the switch, the switch for switching between a sample mode and a hold mode. Each sample and hold circuit also includes a capacitor bank associated with the bootstrap circuit such that a setting of the capacitor bank affects an ON state intrinsic resistance of the switch by affecting the voltage level.Type: ApplicationFiled: December 1, 2011Publication date: June 6, 2013Applicant: CREST SEMICONDUCTORS, INCInventors: Tracy Johancsik, Ryan James Kier, Yusuf Haque
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Publication number: 20130120066Abstract: A reference buffer amplifier within an integrated circuit includes a first output terminal connected to a first bond pad, the first bond pad being connected to a first external pin of the integrated circuit chip, the first external pin to allow an external capacitance to be connected to the output terminal. The reference buffer further includes a variable, settable resistance sub-circuit connected to a second bond pad, the second bond pad also being connected to the first external pin. The resistance sub-circuit is configured to be set to exhibit a resistance value to critically dampen a response of the reference buffer amplifier.Type: ApplicationFiled: November 11, 2011Publication date: May 16, 2013Applicant: CREST SEMICONDUCTORS, INCInventors: Tracy Johancsik, Rex K. Hales, Ryan James Kier, Yusuf Haque
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Patent number: 8344922Abstract: A Digital-to-Analog Converter (DAC) with code independent output capacitance includes circuitry configured to convert a digital input signal to an analog output signal in a manner such that at least one output terminal of the DAC exhibits a constant capacitance value for up to all received values of the digital input signal. A method for converting a digital signal to an analog signal with a DAC includes converting a digital input signal to an analog output signal in a manner such that at least one output terminal of the DAC exhibits a constant capacitance value for up to all received values of the digital input signal.Type: GrantFiled: August 3, 2010Date of Patent: January 1, 2013Assignee: Crest Semiconductors, Inc.Inventors: Ryan James Kier, Paul Talmage Watkins, Yusuf Aminul Haque
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Publication number: 20120032829Abstract: A Digital-to-Analog Converter (DAC) with code independent output capacitance includes circuitry configured to convert a digital input signal to an analog output signal in a manner such that at least one output terminal of the DAC exhibits a constant capacitance value for up to all received values of the digital input signal. A method for converting a digital signal to an analog signal with a DAC includes converting a digital input signal to an analog output signal in a manner such that at least one output terminal of the DAC exhibits a constant capacitance value for up to all received values of the digital input signal.Type: ApplicationFiled: August 3, 2010Publication date: February 9, 2012Applicant: SIFLARE, INC.Inventors: Ryan James Kier, Paul Talmage Watkins, Yusuf Aminul Haque