Patents by Inventor Ryan Jurasek
Ryan Jurasek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11048583Abstract: A novel architecture provides many of the advantages of the array and datapath architecture of DRAM products that do not utilize ECC (error correction code) functionality, while simultaneously allowing the flexible deployment of ECC error correction as needed. Aspects of the disclosure enable the minimization of write and read latency typically introduced by the implementation of ECC error correction. Sharing of circuit components between neighboring memory regions is also introduced, which allows for a reduction in circuit area as well as a reduction in loading on speed-critical data bus wiring, which improves overall performance. A very fast single error correct (SEC) and double error detect (DED) read-out for real-time system-level awareness is also provided.Type: GrantFiled: September 12, 2016Date of Patent: June 29, 2021Assignee: Green Mountain Semiconductor Inc.Inventors: Wolfgang Hokenmaier, Ryan A. Jurasek, Donald W. Labrecque
-
Patent number: 11024355Abstract: An MRAM bitline write control circuit including an MRAM array of a plurality of MTJ cells. Each MTJ cell is connected to a bitline between a bitline transfer gate and a transfer device. Each transfer device is connected to a sourceline and a sourceline transfer gate. A master bitline is connected to each bitline transfer gate. A first bitline control transistor is connected to VDD and to a source follower transistor that is connected to the master bitline and a gate connected to a write 0 bias voltage. A second bitline control transistor is connected to VSS and to the master bitline. A selected MTJ cell is biased to write a 0 when the transfer device, the bitline transfer gate and the source line transfer gate, associated with the selected MTJ cell, are enabled and the first bitline control transistor is enabled to connect the source follower transistor to VDD.Type: GrantFiled: January 31, 2020Date of Patent: June 1, 2021Assignee: International Business Machines CorporationInventors: Kotb Jabeur, Ryan A. Jurasek
-
Patent number: 10818344Abstract: Techniques are disclosed for artificial neural network functionality within dynamic random-access memory. A plurality of dynamic random-access cells is accessed within a memory block. Data within the plurality of dynamic random-access cells is sensed using a plurality of sense amplifiers associated with the plurality of dynamic random-access cells. A plurality of select lines coupled to the plurality of sense amplifiers is activated to facilitate the sensing of the data within the plurality of dynamic random-access cells, wherein the activating is a function of inputs to a layer within a neural network, and wherein a bit within the plurality of dynamic random-access cells is sensed by a first sense amplifier and a second sense amplifier within the plurality of sense amplifiers. Resulting data is provided based on the activating wherein the resulting data is a function of weights within the neural network.Type: GrantFiled: July 22, 2019Date of Patent: October 27, 2020Assignee: Green Mountain Semiconductor, Inc.Inventors: Wolfgang Hokenmaier, Jacob Bucci, Ryan Jurasek
-
Patent number: 10360971Abstract: Techniques are disclosed for artificial neural network functionality within dynamic random-access memory. A plurality of dynamic random-access cells is accessed within a memory block. Data within the plurality of dynamic random-access cells is sensed using a plurality of sense amplifiers associated with the plurality of dynamic random-access cells. A plurality of select lines coupled to the plurality of sense amplifiers is activated to facilitate the sensing of the data within the plurality of dynamic random-access cells, wherein the activating is a function of inputs to a layer within a neural network, and wherein a bit within the plurality of dynamic random-access cells is sensed by a first sense amplifier and a second sense amplifier within the plurality of sense amplifiers. Resulting data is provided based on the activating wherein the resulting data is a function of weights within the neural network.Type: GrantFiled: April 24, 2018Date of Patent: July 23, 2019Assignee: Green Mountain Semiconductor, Inc.Inventors: Wolfgang Hokenmaier, Jacob Bucci, Ryan Jurasek
-
Patent number: 10002658Abstract: A highly configurable, extremely dense, high speed and low power artificial neural network is presented. The architecture may utilize DRAM cells for their density and high endurance to store weight and bias values. A number of primary sense amplifiers along with column select lines (CSLs), local data lines (LDLs), and sense circuitry may comprise a single neuron. Since the data in the primary sense amplifiers can be updated with a new row activation, the same hardware can be reused for many different neurons. The result is a large amount of neurons that can be connected by the user. Training can be done in hardware by actively varying weights and monitoring cost. The network can be run and trained at high speed since processing and/or data transfer that needs to be performed can be minimized.Type: GrantFiled: November 2, 2016Date of Patent: June 19, 2018Assignee: Green Mountain Semiconductor Inc.Inventors: Wolfgang Hokenmaier, Ryan A. Jurasek, Donald W. Labrecque
-
Patent number: 9899087Abstract: An extremely dense, high speed, and low power content addressable DRAM is presented. To enable a parallel searching, a data word to be searched may be driven onto column select lines (CSLs) of a DRAM array. Although two or more primary sense amplifiers typically are not connected at the same time to the same local data line during operation of a DRAM, in various embodiments presented herein, some or all sense amplifiers in a DRAM can be activated simultaneously to enable maximum parallelism with local data line sharing being explicitly allowed. Using this architecture, a data word can be simultaneously searched in all banks and with multiple wordlines. Since no input/output transactions are required and no data needs to be driven from the bank during execution of a search, overall current, and thus power usage, can be reduced.Type: GrantFiled: November 7, 2016Date of Patent: February 20, 2018Assignee: Green Mountain Semiconductor Inc.Inventors: Wolfgang Hokenmaier, Ryan A. Jurasek, Donald W. Labrecque, Aaron D. Willey
-
Patent number: 9036408Abstract: Methods, circuits, and systems for phase change memories. A matching bit line, on which no data-containing PCM cells have been selected, is used to cancel out time-dependent current components due to parasitic capacitive and leakage resistance loading of bit lines. This can effectively allow direct comparison of the current from the phase change memory cell to the desired reference current, at a time before the voltage of the first bit line permits stable operations using DC comparison.Type: GrantFiled: August 27, 2013Date of Patent: May 19, 2015Inventors: Ryan Jurasek, Aaron Willey
-
Publication number: 20150078076Abstract: Methods and systems for time-based cell decoding for PCM memory. Generally, the higher the PCM element resistance, the longer it takes for a read output to change state. PCM memory output is determined using differentiated timings of read outputs changing state, rather than differentiated values of read outputs. In some single-bit single-ended sensing embodiments, a reference, with resistance between the resistances corresponding to a pair of adjacent logical states, is stored in multiple reference cells; a “vote” unit emits a clock signal when a majority of the reference cell read outputs transition at the vote unit. Timing units produce different binary outputs depending on whether a data read output or the clock signal changes state first at the timing unit. Time-based decoding provides advantages including improved temperature and drift resilience, improved state discrimination, improved reliability of multibit PCM, and fast and reliable sensing.Type: ApplicationFiled: April 1, 2014Publication date: March 19, 2015Applicant: BEING ADVANCED MEMORY CORPORATIONInventors: Aaron D. Willey, Ryan Jurasek
-
Patent number: 8908417Abstract: Methods and systems for phase change memories and arrays with improved write characteristics. If a data word can be more efficiently written by e.g. exchanging SETs and RESETs, it is written as such on the fly, and e.g. a bit of overhead is written to indicate the transformation. This has a surprising synergy with phase change memory as SET operations usually take longer and consume more power than do RESET operations. In one sample embodiment of multilevel phase change memory, states intermediate between SET and RESET can be even less desirable to write than SETs, as they take more precision than do the extreme states of SET and RESET, so that a desirable transformation can be to exchange intermediate states for extreme states.Type: GrantFiled: April 8, 2014Date of Patent: December 9, 2014Inventors: Yuanxing Li, Van Butler, Ryan Jurasek
-
Patent number: 8908427Abstract: Methods and systems for time-based cell decoding for PCM memory. Generally, the higher the PCM element resistance, the longer it takes for a read output to change state. PCM memory output is determined using differentiated timings of read outputs changing state, rather than differentiated values of read outputs. In some single-bit single-ended sensing embodiments, a reference, with resistance between the resistances corresponding to a pair of adjacent logical states, is stored in multiple reference cells; a “vote” unit emits a clock signal when a majority of the reference cell read outputs transition at the vote unit. Timing units produce different binary outputs depending on whether a data read output or the clock signal changes state first at the timing unit. Time-based decoding provides advantages including improved temperature and drift resilience, improved state discrimination, improved reliability of multibit PCM, and fast and reliable sensing.Type: GrantFiled: March 24, 2014Date of Patent: December 9, 2014Inventors: Aaron D. Willey, Ryan Jurasek
-
Patent number: 8897063Abstract: Methods and systems for multi-bit phase change memories. Using differential sensing for memory reads provides advantages including improved temperature and drift resilience, improved state discrimination and increased storage density.Type: GrantFiled: March 24, 2014Date of Patent: November 25, 2014Inventors: Ryan A. Jurasek, Aaron D. Willey
-
Patent number: 8891294Abstract: Methods and systems for multi-bit phase change memories. Using differential sensing for memory reads provides advantages including improved temperature and drift resilience, improved state discrimination and increased storage density.Type: GrantFiled: April 24, 2013Date of Patent: November 18, 2014Assignee: Being Advanced Memory CorporationInventors: Ryan A. Jurasek, Aaron D. Willey
-
Patent number: 8879344Abstract: Methods and systems for time-based cell decoding for PCM memory. Generally, the higher the PCM element resistance, the longer it takes for a read output to change state. PCM memory output is determined using differentiated timings of read outputs changing state, rather than differentiated values of read outputs. In some single-bit single-ended sensing embodiments, a reference, with resistance between the resistances corresponding to a pair of adjacent logical states, is stored in multiple reference cells; a “vote” unit emits a clock signal when a majority of the reference cell read outputs transition at the vote unit. Timing units produce different binary outputs depending on whether a data read output or the clock signal changes state first at the timing unit. Time-based decoding provides advantages including improved temperature and drift resilience, improved state discrimination, improved reliability of multibit PCM, and fast and reliable sensing.Type: GrantFiled: April 1, 2014Date of Patent: November 4, 2014Inventors: Aaron D. Willey, Ryan Jurasek
-
Publication number: 20140321200Abstract: Methods and systems for time-based cell decoding for PCM memory. Generally, the higher the PCM element resistance, the longer it takes for a read output to change state. PCM memory output is determined using differentiated timings of read outputs changing state, rather than differentiated values of read outputs. In some single-bit single-ended sensing embodiments, a reference, with resistance between the resistances corresponding to a pair of adjacent logical states, is stored in multiple reference cells; a “vote” unit emits a clock signal when a majority of the reference cell read outputs transition at the vote unit. Timing units produce different binary outputs depending on whether a data read output or the clock signal changes state first at the timing unit. Time-based decoding provides advantages including improved temperature and drift resilience, improved state discrimination, improved reliability of multibit PCM, and fast and reliable sensing.Type: ApplicationFiled: March 24, 2014Publication date: October 30, 2014Applicant: Being Advanced Memory CorporationInventors: Aaron D. Willey, Ryan Jurasek
-
Patent number: 8854875Abstract: Methods and systems for time-based cell decoding for PCM memory. Generally, the higher the PCM element resistance, the longer it takes for a read output to change state. PCM memory output is determined using differentiated timings of read outputs changing state, rather than differentiated values of read outputs. In some single-bit single-ended sensing embodiments, a reference, with resistance between the resistances corresponding to a pair of adjacent logical states, is stored in multiple reference cells; a “vote” unit emits a clock signal when a majority of the reference cell read outputs transition at the vote unit. Timing units produce different binary outputs depending on whether a data read output or the clock signal changes state first at the timing unit. Time-based decoding provides advantages including improved temperature and drift resilience, improved state discrimination, improved reliability of multibit PCM, and fast and reliable sensing.Type: GrantFiled: April 1, 2014Date of Patent: October 7, 2014Inventors: Aaron D. Willey, Ryan Jurasek
-
Patent number: 8837211Abstract: The present application discloses phase-change memory architectures and methods, in which an additional test is performed, after the normal power-valid signal, to assure that the phase-change memory components which are used for storing configuration data are able to operate correctly. Surprisingly, the inventor has discovered that this additional test is highly desirable when using phase-change memory for configuration data.Type: GrantFiled: April 24, 2013Date of Patent: September 16, 2014Inventor: Ryan Jurasek
-
Patent number: 8830731Abstract: Methods and systems for phase change memories and arrays with improved write characteristics. If a data word can be more efficiently written by e.g. exchanging SETs and RESETs, it is written as such on the fly, and e.g. a bit of overhead is written to indicate the transformation. This has a surprising synergy with phase change memory as SET operations usually take longer and consume more power than do RESET operations. In one sample embodiment of multilevel phase change memory, states intermediate between SET and RESET can be even less desirable to write than SETs, as they take more precision than do the extreme states of SET and RESET, so that a desirable transformation can be to exchange intermediate states for extreme states.Type: GrantFiled: April 1, 2014Date of Patent: September 9, 2014Inventors: Yuanxing Li, Van Butler, Ryan Jurasek
-
Patent number: 8830741Abstract: Methods and systems for time-based cell decoding for PCM memory. Generally, the higher the PCM element resistance, the longer it takes for a read output to change state. PCM memory output is determined using differentiated timings of read outputs changing state, rather than differentiated values of read outputs. In some single-bit single-ended sensing embodiments, a reference, with resistance between the resistances corresponding to a pair of adjacent logical states, is stored in multiple reference cells; a “vote” unit emits a clock signal when a majority of the reference cell read outputs transition at the vote unit. Timing units produce different binary outputs depending on whether a data read output or the clock signal changes state first at the timing unit. Time-based decoding provides advantages including improved temperature and drift resilience, improved state discrimination, improved reliability of multibit PCM, and fast and reliable sensing.Type: GrantFiled: August 27, 2013Date of Patent: September 9, 2014Inventors: Aaron D. Willey, Ryan Jurasek
-
Publication number: 20140211556Abstract: Methods and systems for phase change memories and arrays with improved write characteristics. If a data word can be more efficiently written by e.g. exchanging SETs and RESETs, it is written as such on the fly, and e.g. a bit of overhead is written to indicate the transformation. This has a surprising synergy with phase change memory as SET operations usually take longer and consume more power than do RESET operations. In one sample embodiment of multilevel phase change memory, states intermediate between SET and RESET can be even less desirable to write than SETs, as they take more precision than do the extreme states of SET and RESET, so that a desirable transformation can be to exchange intermediate states for extreme states.Type: ApplicationFiled: April 1, 2014Publication date: July 31, 2014Applicant: Being Advanced Memory CorporationInventors: Yuanxing Li, Van Butler, Ryan Jurasek
-
Publication number: 20140211554Abstract: Methods and systems for phase change memories and arrays with improved write characteristics. If a data word can be more efficiently written by e.g. exchanging SETs and RESETs, it is written as such on the fly, and e.g. a bit of overhead is written to indicate the transformation. This has a surprising synergy with phase change memory as SET operations usually take longer and consume more power than do RESET operations. In one sample embodiment of multilevel phase change memory, states intermediate between SET and RESET can be even less desirable to write than SETs, as they take more precision than do the extreme states of SET and RESET, so that a desirable transformation can be to exchange intermediate states for extreme states.Type: ApplicationFiled: April 8, 2014Publication date: July 31, 2014Applicant: BEING ADVANCED MEMORY CORPORATIONInventors: Yuanxing Li, Van Butler, Ryan Jurasek